Suresh Babu has a Bachelor’s degree in Engineering with specialization in Instrumentation and Control Engineering from Madurai Kamaraj University, India. He started his career building hardware prototypes containing 16 bit microcontrollers and realized RTL designs of IEEE papers and concepts published in the IEEE Magazines into mini FPGA’s for Educational and Training purposes. These formed the formative years for a solid foundation in Hardware Concepts. This enabled him to easily adapt into the roles of aVerification Engineer at GDA Technologies and where he flourished to become a Project Lead leading small teams to verify IP, Subsystem and SoC’s containing complex protocols like USB, PCIe and High Speed Memory Interfaces. During his GDA he has also seen the evolution of different methodologies like eRM and OVM and applying them successfully on client projects.
He is a key member of T&VS Technical and Delivery team and performs the role of a Solutions Architect for all Key Customer Engagements related to the APAC Region (Korea and Japan). He also plays a key role in defining the T&VS VIP Architecture and overseeing the VIP program within T&VS. Currently he is leading a large team and performing Verification of an Advanced Memory Subsystem for a handset application manufacturing OEM and he has architected the complete flow from Specification to Signoff. He also leads the EDA Productivity Tools BU where he has played an important role in defining the requirements of the productivity tool (asureRAL, asureRUN, asureCode) and guiding the team to complete it. He has overall industry experience of 16 Years and also his articles have been published in Mentor Graphics Technical Publications.