Intel present “CM” Domain Specific Language to exploit parallelism at Multicore Challenge 2014

At this year’s Multicore Challenge (2014) conference, David Stuttard from Intel will be providing an overview of “CM”, a low level proprietary Domain Specific Language (DSL) that supports a different model for parallelism that provides direct support for hardware features particularly suited to media and compute tasks. In particular it allows lower level and more flexible access to the hardware’s parallelism allowing different parallelisation within the same algorithm as often required by for instance modern video codecs.

In his presentation, David will describe some of these hardware features, how the CM language supports them, how the programmer can make use of these features and how it sits within a wider Media Developer Framework runtime environment for multicore programming.

About David Stuttard

David has over 20 years of experience developing multicore tools and architectures. David was one of the original architects for the PixelFusion massively parallel GPU as well as developing simulation and programming tools for this architecture. Subsequently David was one of the co-developers of the ClearSpeed multicore accelerator processors for which he designed a programming language and associated compiler tools.

David also developed LLVM based OpenCL and OpenGLES compiler tools for the ZiiLABS range of ARM based processors for embedded systems (targeting the parallel GPU processor designed by ZiiLABS integrated into the SoC). David is currently at Intel working on parallel languages and compilers for GPU architectures

Additional Information

For additional information on the Multicore Challenge Conference and Tool Demonstrations (23 September, 2014 | Bristol, UK) Click Here.


2014-09-10T11:24:30+00:00 10th September, 2014|Active Event, Multicore|
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.