Can Verification Meet In The Middle?

The semiconductor industry has long considered verification to be a bottom-up process, but there is now a huge push to develop standards for top-down verification. Meet-in-the-middle is about making sure that the two verification flows work together.

This article from Semiengineering captures the conversation between Synopsys, Cadence, Mentor Graphics and Agnisys on how does the verification overcomes the challenges to meet comfortably in the middle.

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Find out how T&VS Hardware Verification services address the challenges of verification methodologies.

2016-07-13T06:37:43+00:0013th July, 2016|Blog, Thought Leadership|