ASIC design engineer – JobCode: HWDUSA020518_37 2018-05-02T14:30:18+00:00


Job Title:

ASIC design engineer

Job Code:


Job Description

  • ASIC frontend development.
  • Logic design, RTL coding, verification, synthesis, and timing closure.
  • Hardware description languages (Verilog, System Verilog and VHDL).
  • AMBA bus standards such as AXI, AHB, and ACE
  • Synopsys DC/PrimeTime or similar tools.
  • Scripting/programming in C/C++, Tcl, Perl/Csh.

Minimum Qualifications: RTL design

3+ years of industry experience in 1 or more of the following technical disciplines:

  • SoC Design(ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI)
  • RTL Design(Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency)
  • Low Power Design(clock gating, power gating, power grids, Power Artist, UPF, CPF)
  • High-Speed DDR Controller(Memory Controller, CPU, SRAM & L3 Cache, x86 or ARM CPU/bus architecture)
  • Audio Codec ASIC Hardware(Audio DSP Implementation, Audio Algorithm, Low-Power Voice/Audio Activation, Noise Cancellation)
  • Graphic ASIC Hardware(GPU or CPU cores, DX9/10/11 level graphics HW development)
  • Multimedia/Camera Imaging/Video(Image processing algorithms, ASIC Design, RTL Coding, JPEG, C/C++/SystemC, Modelsim, Synopsys DC, LEC, Spyglass)
  • Physical Layer Design(PHY, USB, HDMI, DDR, MIPI)
  • SerDes Application(PHY Layer Protocol, SerDes PHY, ASIC EDA Models, Cadence Schematics)
  • Digital Design for Mixed Signal ASICs(PLL, Phase-Lock-Loop, LNA, OpAmp, ADC-DAC)

Good to have

From scratch RTL design for any/some of the following:

Note: IP integration of various components or modification of previously designed components (unless it is a major change that shows understanding for the below) is not very relevant

  • Complex state machine design
  • Memory subsystem with multiple banking multiple reports, crossbar connection to computing elements
  • 3-D, 4-D descriptor based DMA controller with out of order responses
  • The DSP functionality knowledge, integer/float multiply – accumulate, and nonlinear functions such as sigmoid, relu, tanh, quantization, reduction
  • AXI4 fabric with out-of-order interleaved requests/responses (i.e. full protocol)
  • Tools: UVM, System Verilog, Perl, all Cadence front/back end tools


  • 3+ years of industry experience


  • Highly competitive to match experience and capability
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