ASIC Verification Engineer – USA 2018-02-26T09:16:34+00:00

Job Location: Mountain View, CA

Job Type: Contract / Full Time

Experience required:  5 to 10+ years

 

Skills Required:

  • Minimum 5+ years experience required in ASIC Verification
  • Verilog and C/C++ coding a must
  • Makefiles, Perl scripting a must
  • Chip/full system level ASIC Verification skills, and debug skills a must
  • Debug using waveforms a must, Verdi source level debug a plus
  • Board level debug with logic analyzers, scopes desirable
  • Experience working with X 64 architecture a great plus
  • Experience working with PCI-Express a plus
  • System level knowledge a must
  • System is defined as a test bench containing (CPU + GPU + multi-media engines + Southbridge) with hardware based coherency
  • System could be a simulation test bench, emulation test bench or a board
  • System level knowledge does not mean signal integrity checking, electrical checks, EMC checks, thermal checks, ATPG testing on a board
  • Tests will be written in C/C++, compiled for CPU and will be run on simulation/emulation/board unchanged
  • Block/unit level verification skills using OVM/UVM knowledge desirable (not required)

Package

  • Highly competitive to match experience and capability

How To Apply

Send your CV to [email protected]

 

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.