- Experience with System Verilog, UVM.
- Experience with synthesizable Verilog
- Excellent debugging skills with both C and Verilog.
- Experience with MIPI, LPDDR, PCIe, OCP VIP or protocol is plus
- Experience with emulation and bring-up is a plus
- PCIe PHY experience
- Create and modify block-level testbenches
- Create random and directed testcases for the device under test
Availability: 1-2 Weeks
Preference: US Citizens,Green Card holders, H1 B, H4 holders(Currently in US)
Experience: 5-10 Years
- Highly competitive to match experience and capability
How To Apply
Send your CV to [email protected]