Design Verification Engineer
- BSEE/MSEE and experience in Verification and/or Design including the following
- Hardware Verification Languages including System Verilog, Scripting Test Benches, OVM/UVM Methodologies and System Verilog Assertions.
- Digital Design and HDL’s such as Verilog, VHDL and System Verilog.
- Scripting Languages such as Perl/tcl/Python/Gmake.
- Verification of SoC’s with CPU, DSP or Micro-Controller Cores.
- Simulation Tools such as Simvision and Verdi.
- C++ with the ability to understand Reference Models.
- Solid understanding of Object Oriented Programming (OOP) Principles.
Additional Preferred Qualifications:
- Understanding of Bus Architectures (AXI or similar), Baseband/RFIC Interfaces, Network-on-Chip, various CPU/DSP Architectures, Multi-Domain Clocking and Power Management.
- Experience in developing and maintaining UPF Files for Power Analysis.
- Verification of Mixed-Signal IP’s such as PLL’s and LDO’s.
- Understanding of Pre-Silicon Emulation for a Multi-Million Gate Count SoC.
- Experience with tools like Palladium/Zebu.
- Santa Clara, CA
- 5+ years ( Entry level do not apply )
- Highly competitive to match experience and capability