DFT Engineer – JobCode: HWVALL230118_012018-03-01T09:08:33+00:00

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Job Title:

DFT Engineer

Job Code:

HWVALL230118_01

Job Description

Professionals with any of the following skills required:

  • Scan Insertion
    • A good knowledge in scan insertion basics with any of the tools like DFT Compiler, Tessent Scan, RTL Compiler
    • Good knowledge in analyzing the DFT-DRC
    • Good knowledge in strategies for addressing multi clock domain based designs.
    • Good knowledge in compression techniques EDT, DFTMAX, ET
    • Good knowledge in implementing OCC for the at-speed scan.
    • Good knowledge on the small delay defect, path delay test and cell aware test.
    • Exposure to Power aware scan implementations and concepts with upf/cpf
  • ATPG :
    • Hands on with Tessent TestKompress, Tetramax dofile development and knowledge on commands.
    • Excellent debug capabilities on the DRC violations related to OCC, EDT, LPCT for chain tracing and pattern generation
    • Good knowledge on the procedure/stil file for generating single, multiple capture sequences for relevant scan testing
    • Knowledge on tracing the C, D violations for coverage and pattern volume.
    • Exposure to NCP, fault grouping based on clock domains and targeting inter clock domain, synchronous intra clock domain faults.
  • Test Controller :
    • Excellent knowledge on TAP controller compliance with IEEE 1149.1 and 1149.6
    • Knowledge on Functionality of WTAP, P1500 protocols
    • Exposure to multiple testmode operations to control different peripherals through TAP or custom boot strap sequences.
    • Knowledge on iJTAG is a value addition
  • MBIST :
    • Good knowledge in MBIST concept and Algorithms.
    • Good RTL debug skills to understand and do necessary RTL coding for MBIST integration.
    • Good knowledge on the memory types and architectures with scrambling/descrambling functionalities of memory models.
    • SMS (Star Memory System), Tessent MBIST command and tool exposures.
    • Good implementation skills of SMS with Integrator
  • LINT :
    • Good knowledge on DFT Lint rules.
    • Exposure to spyglass, Leda
    • Good understanding of DFT related RTL coding constructs
  • STA :
    • Good exposure on writing design constraints (SDC) for scan modes.
    • Good knowledge on schmoo plots and analyzing them.
    • Good knowledge on hold/setup timing closures for scan
  • Simulation :
    • Gate Level Simulation (GLS) for scan chain, scan patterns with parallel and serial modes.
    • Good track of records on tracing X’s in simulation and identifying the issues.
    • Good track of records on debugging memory failures during memory bist simulation.
  • Formal Verification :
    • Knowledge on formal verification with Formality/Skyglass or conformal.
  • Scripting :
    • Knowledge on perl, TCL, shell scripting is a must.

Location

  • India (Chennai/Bangalore/Hyderabad), UK, USA, Malaysia and Singapore.

Experience

  • Fresher to Any Experience Level

Package

  • Highly competitive to match experience and capability
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