DFT Engineer – JobCode: HWVALL230118_01 2018-03-01T09:08:33+00:00

Careers

Job Title:

DFT Engineer

Job Code:

HWVALL230118_01

Job Description

Professionals with any of the following skills required:

  • Scan Insertion
    • A good knowledge in scan insertion basics with any of the tools like DFT Compiler, Tessent Scan, RTL Compiler
    • Good knowledge in analyzing the DFT-DRC
    • Good knowledge in strategies for addressing multi clock domain based designs.
    • Good knowledge in compression techniques EDT, DFTMAX, ET
    • Good knowledge in implementing OCC for the at-speed scan.
    • Good knowledge on the small delay defect, path delay test and cell aware test.
    • Exposure to Power aware scan implementations and concepts with upf/cpf
  • ATPG :
    • Hands on with Tessent TestKompress, Tetramax dofile development and knowledge on commands.
    • Excellent debug capabilities on the DRC violations related to OCC, EDT, LPCT for chain tracing and pattern generation
    • Good knowledge on the procedure/stil file for generating single, multiple capture sequences for relevant scan testing
    • Knowledge on tracing the C, D violations for coverage and pattern volume.
    • Exposure to NCP, fault grouping based on clock domains and targeting inter clock domain, synchronous intra clock domain faults.
  • Test Controller :
    • Excellent knowledge on TAP controller compliance with IEEE 1149.1 and 1149.6
    • Knowledge on Functionality of WTAP, P1500 protocols
    • Exposure to multiple testmode operations to control different peripherals through TAP or custom boot strap sequences.
    • Knowledge on iJTAG is a value addition
  • MBIST :
    • Good knowledge in MBIST concept and Algorithms.
    • Good RTL debug skills to understand and do necessary RTL coding for MBIST integration.
    • Good knowledge on the memory types and architectures with scrambling/descrambling functionalities of memory models.
    • SMS (Star Memory System), Tessent MBIST command and tool exposures.
    • Good implementation skills of SMS with Integrator
  • LINT :
    • Good knowledge on DFT Lint rules.
    • Exposure to spyglass, Leda
    • Good understanding of DFT related RTL coding constructs
  • STA :
    • Good exposure on writing design constraints (SDC) for scan modes.
    • Good knowledge on schmoo plots and analyzing them.
    • Good knowledge on hold/setup timing closures for scan
  • Simulation :
    • Gate Level Simulation (GLS) for scan chain, scan patterns with parallel and serial modes.
    • Good track of records on tracing X’s in simulation and identifying the issues.
    • Good track of records on debugging memory failures during memory bist simulation.
  • Formal Verification :
    • Knowledge on formal verification with Formality/Skyglass or conformal.
  • Scripting :
    • Knowledge on perl, TCL, shell scripting is a must.

Location

  • India (Chennai/Bangalore/Hyderabad), UK, USA, Malaysia and Singapore.

Experience

  • Fresher to Any Experience Level

Package

  • Highly competitive to match experience and capability
We're hiring

Apply for this position

  • Accepted file types: doc, pdf.
  • This field is for validation purposes and should be left unchanged.

More Opportunities

View all Career Opportunities

Share this Job

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.