- RTL partitioning, synthesis, design rule checks, constraint development and validation, timing analysis, formal verification
- This position requires detailed knowledge of ASIC design including RTL design, synthesis, and timing closure.
- Specific experience with Synopsys DCT/DCG, LINT, PTSI, and Verilog/VHDL is required.
- High-level Synthesis or HLS.
- Having good understanding on RTL and HLS will be required for this req.
- Experience with VLSI designs targeting 45nm or below preferred.
- Formal verification, LEC preferred
Education: Required: Bachelor’s, Electrical Engineering
Work Location: California – San Diego
Package: Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]