Formal Verification CAD engineer – JobCode: HWVUSA061117_13

Job Overview:

  • Formal Verification CAD Engineers are responsible for developing, implementing, and deploying automated formal verification methodologies and tool flows that are used to validate a multitude of wireless chips and IP cores/blocks.
  • As part of the Mobile and Computing engineering team, this position plays a critical role in driving next-generation formal and static verification methodologies through the deployment of semi- and full-custom EDA tools that are used widely across the globe by the various ASIC digital design teams.
  • As a key member of the EDA CAD verification design automation team, will develop and contribute directly to technical aspects of many advanced formal verification methodologies and initiatives.
  • Key areas of focus in low power, connectivity checks, sequential equivalence checking (SEC), and formal coverage.
  • Work closely with cross-functional teams by leveraging domain-specific expertise and sharing/coordinating prototyping efforts, testing, and support.
  • In addition to maintaining and enhancing our Formal Verification flow, you will contribute in developing, maintaining and enhancing our Linting and Clock Domain Crossing (CDC) applications for SoC projects across multiple sites.
  • Responsible for developing, implementing, and deploying advanced verification methodologies and flow automations across all chips and IP cores/block.

Minimum Qualifications:

  • Experience evaluating, designing, and deploying EDA tools in the area of formal verification, and static verification Prior experience with formal tools like Jasper, IFV , VC-Formal and formal verification apps (reset, CSR, UNR, connectivity, x-prop etc…)
  • Expertise in power domain checking tools (CLP, MVRC, VSILP) is highly desirable.
  • Good knowledge of Object Oriented Hardware Verification Languages (OO-HVLs) such as SystemVerilog, as well as industry standard hardware description languages (HDLs) like Verilog/VHD Good knowledge in temporal logic assertion-based languages such as SVA.
  • Experience in RTL synthesis (Design Compiler, RTL Compiler, etc.) is useful.

Preferred Qualifications:

  • Strong programming capabilities in C/C++, Perl, python, Tcl, and Java.
  • Strong Object Oriented programming skills is a big plus

Education: Required: Bachelors of Science degree in Computer Engineering, Computer Science, or Electrical Engineering.
Preferred: Masters of Science degree in Computer Engineering, Computer Science, or Electrical Engineering.

Work Location: California – San Diego

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]