FPGA Design

Job Code: HWDIND_02

Job Description:

  • Master’s/Bachelor’s degree in Electrical/Electronic engineering with 3-5 years’ experience in FPGA design/STA
  • Experience with design flows utilizing Unix/Linux, EDA Tools and Verilog/VHDL
  • Very good understanding of timing concepts,
  • Experience in Static Timing Analysis, Delay Calculation, Timing Reporting, Constraints handling
  • Scripting and automation skills in Perl and TCL
  • Candidate must possess passion and commitment for completing projects on time.
  • Candidate must have excellent oral and written communication skills.
  • Understanding of FPGA architectures would be useful.

Location: Hyderabad

Experience: 3 to 5 years

Package

  • Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]