FPGA Design / Lead – HWDIND091117_29

Job Description:

  • Coding : C, VHDL, Verilog / RTL Coding, Timing Synthesis, HIL Simulation
  • Tools : Xilinx Vivado Tools for Kintex / Artix Family, Matlab System Generator Expertise is Must
  • I/O Interfaces : JESD, AIC Related Antenna Interfaces expertise in LTE,
  • Designs : Experience in LTE / Any broad band development expertise, Multi-Clock domain development, Optimization and debugging expertise.
  • Technologies Expertise : LTE, Mixers / PLL / DPLL, ADC / DAC Interconnect, High Speed Inter-Processor Interconnect Expertise

Location: Bangalore

Experience: 5+ Years

No of Positions : 3

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]