Functional Design Verification Engineer – JobCode: HWDUSA061117_30

Job Overview:

  • Work on design and verification methodology for various ASIC designs using multiple techniques (simulation, model checking, assertion-based verification, equivalence checking, and theorem proving).
  • Projects include functional design verification, protocol verification, post-silicon debugging, clock domain crossing verification, deadlock detection, CPU verification, and developing new applications by leveraging existing design, simulation, and formal verification tools available in the industry.

Minimum Qualifications:

  • Strong critical thinking and problem solving skills.
  • General knowledge in ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc.
  • Familiar with the design and assertion languages: VHDL, Verilog, System Verilog, UPF, CLP, and System Verilog Assertions (SVA).
  • Experience in functional verification EDA tools: VCS, IUS, ModelSim, Jasper, 0-in, IFV, OneSpin, SLEC, etc is highly desired.

Preferred Qualifications:

  • Familiar with programming languages: C, C++, and SystemC.
  • Scripting and automation skills: Unix/Linux shell programming, Perl, Java, Makefile, XML, XML DOM, XPath, XSLT, revision management (e.g. CVS, DesignSync, Subversion) is a plus.

Education: Required: Bachelor’s, Electrical Engineering or equivalent experience Preferred: Master’s or equivalent experience

Work Location: California – San Diego

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]