Junior SoC DFT Engineer 2017-04-28T09:37:18+00:00

The role involves covering primary DFT activities of 

  • Architecture
  • RTL
  • MBIST/BISR insertion and simulation
  • Scan insertion
  • AMS simulation
  • STA test constraints
  • debug and vector generation
  • ATE test program development

The following are required:

  • Degree in Electrical Engineering, Computer Engineering or other relevant technical area
  • at least 1 year of full time DFT experience
  • some exposure to Verilog and/or VHDL RTL coding
  • TCL scripting
  • Some exposure to DFT concepts
  • At least one scripting language such as Perl or Python
  • Knowledge of IEEE1149.1, IEEE1500, IEEE1687
  • Some exposure to DFT verification
  • Very good collaboration and communication skills

The following are desirable but not essential

  • Scan insertion, preferably on the Synopsys flow
  • ATPG generation (preferably with Synopsys TetraMAX) and validation
  • Direct experience on Silicon debugging/bring-up of DFT tests
  • MBIST insertion and validation
  • PHY DFT verification
  • ATE experience
  • Boundary Scan insertion
  • Design Synthesis
  • Verification experience
  • Physical Design exposure

Experience: 3+ Years

Location: UK

Package:

  • Highly competitive to match experience and capability

How To Apply: Send your CV to [email protected]

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.