Lead Physical Design Engineer – JobCode: HWDUSA161017_27

Job Overview:

Candidate will handle all aspects of SOC implementation from netlist to final gds including floor-planning, partitioning, place & route (P&R), timing optimization, scan mode timing, clock tree insertion, and static timing analysis (STA). You will also be responsible for power grid analysis, signal integrity analysis, and physical, electrical, and formal verification.

Minimum Qualifications:

Must possess 10+ years of hands on experience in  P&R from Netlist to GDS including timing closure and Physical verification.

  • Power user of industry standard Physical Design & Verification tools. FirstEncounter,ICC2 etc.
  •  Strong hands-on experience in floor planning, clock tree synthesis, timing closure, signal integrity, IR drop analysis, ECO implementation, and physical design verification
  •  Experience in Technologies: 28nm, 14nm,10nm
  •  Solid Understanding of scripting languages such as Perl/Tcl.
  •  Working knowledge of Extraction and STA methodology and tools.
  •  Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
  •  Excellent verbal and written communication skills are required.
  •  Excellent interpersonal and analytical skills with the ability to work independently.
  •  Highly motivated, excellent team player, product and customer oriented.
  •  Self Motivator and excellent problem solving skills.

Keywords:

Primetime clock tree Timing Closure, Constraints, Debug

Work Location: Santa Clara, CA

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]