Networking Chip Verification Engineers2017-06-22T11:39:05+00:00

Job Description:

Engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC:

  • Traffic Manager
  • Serdes, PCIE protocols, MAC protocols
  • Packet Classification (Layer 2 classification experience is big plus)
  • Algorithmic Search Units
  • Execution Units

Experience: 5+ Years

Location: UK and Bangalore

Package:

  • Highly competitive to match experience and capability

How To Apply: Send your CV to [email protected]