- Candidate should have good understanding of processor architecture, Micro architecture and cache coherency.
- A sound understanding of bus protocols such as PCIe is preferred.
- Good knowledge in C/ C++/ System Verilog (UVM/OVM) and good scripting knowledge in perl/ python is must for this position.
- He/She should have good understanding of VHDL and excellent debug skills.
- Ability to adapt new methodology and ramp up in a short time would be considered and ability to understand Micro Architecture and specifications of the design under test is also required
Number of Positions: 5
Work Location: Bangalore
- Highly competitive to match experience and capability
How To Apply: Send your CV to [email protected]