RTL Design Engineer
- Working experience in block/subsystem/SOC integration
- Experience in designing and RTL coding using Verilog /System Verilog/VHDL.
- Experience in Equivalence checks
- Design QC using lint/CDC/DFT
- Compile , elaboration and simulations for QC. Experience with VCS, Verdi, and Spyglass.
- Understanding of SoC Architectures, Peripherals, Buses/Interconnects and Power Management.
- Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip ) and ARM CPU Architectures.
- Experience in writing functional design doc and/or functional specifications.
- Experience in synthesis using Synopsys Design Compiler ( DC) and developing timing constraints ( SDC) and Timing analysis.
- Experience in developing/understanding of ECOs
- Working experience in teams with collaboration of effort between Verification, Physical Design and DFT Additional Qualifications (preferred)
- Understanding of DFT Methodologies, Formal Verification Tools and Physical Design.
- Experience in RTL integration tools like Magillem is added advantage.
- Working experience in the following fields o RAM memory controller o PHYs o Interconnect bus architecture •
- High speed serial protocols like PCIe, USB, Unipro, etc
- Familiarity with scripting languages likes Perl, Phython
- Team player, can-do attitude is desirable.
- 4+ – 10 years
- Highly competitive to match experience and capability