RTL Logic and Verification Engineer (pre-silicon)
- Develop behavioural and structural RTL codes for block level design.
- Experienced in System Verilog and OVM/UVM
- Validate SOC/ASIC integration and functionality
- Develop test environment, test bench, validation methodology and test plan.
- Familiar with RTL Linting, Spyglass, CDC.
- Familiar with industry standard bus interface and protocol
- 3+ Years
- Highly competitive to match experience and capability