Senior Design/Verification Engineer, ASIC – JobCode: HWVSWE_100518_01 2018-05-10T11:06:54+00:00

Careers

Job Title:

Senior Design/Verification Engineer, ASIC

Job Code:

HWVSWE_100518_01

Job Description

  • You will work with development of 5G radio base stations.
  • You will work with IP block design and some IP verification in digital ASIC projects.
  • The goal of the position is to develop IPs and to verify that the functional requirements of the blocks are fulfilled before tape-out.
  • The work will be carried out in cooperation with other ASIC designers and verification engineers.

Competence/Experience – Mandatory:

  • Long experience from working with ASIC design and verification
  • Very good knowledge of programming in VHDL and Verilog/System Verilog
  • Experience in hardware design/systemization/design methodology
  • Experience in using the System Verilog/UVM tools and methodology
  • Knowledge of constrained random methodology, dedicated test-vectors and assertions
  • Scripting in Perl, Python and/or TCL
  • Experiences from working with synthesis
  • Experience from working with Spyglass
  • Knowledge of equivalence check

Competence/Experience – Optional:

  • Knowledge of SW design for an embedded environment
  • Knowledge in programming C, C++ and System C
  • Experience in system level verification
  • Knowledge about Formal verification
  • Experience from working with LTE/WCDMA and/or GSM systems
  • Experience in agile ways of working

Location

  • Sweden

Experience

  • 10+ Years

Package

  • Highly competitive to match experience and capability
We're hiring

Apply for this position

  • Accepted file types: doc, pdf.
  • This field is for validation purposes and should be left unchanged.

More Opportunities

View all Career Opportunities

Share this Job

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.