Senior Design/Verification Engineer, ASIC
- You will work with development of 5G radio base stations.
- You will work with IP block design and some IP verification in digital ASIC projects.
- The goal of the position is to develop IPs and to verify that the functional requirements of the blocks are fulfilled before tape-out.
- The work will be carried out in cooperation with other ASIC designers and verification engineers.
Competence/Experience – Mandatory:
- Long experience from working with ASIC design and verification
- Very good knowledge of programming in VHDL and Verilog/System Verilog
- Experience in hardware design/systemization/design methodology
- Experience in using the System Verilog/UVM tools and methodology
- Knowledge of constrained random methodology, dedicated test-vectors and assertions
- Scripting in Perl, Python and/or TCL
- Experiences from working with synthesis
- Experience from working with Spyglass
- Knowledge of equivalence check
Competence/Experience – Optional:
- Knowledge of SW design for an embedded environment
- Knowledge in programming C, C++ and System C
- Experience in system level verification
- Knowledge about Formal verification
- Experience from working with LTE/WCDMA and/or GSM systems
- Experience in agile ways of working
- 10+ Years
- Highly competitive to match experience and capability