Senior Verification Engineer – JobCode: HWVKOR141217_01

Job Description:

  • Working experience in verification and integration activities including but not limited to testplan development, test writing, debug, integration and familiar with verification methodologies such as UVM.
  • Excellent Programming skills in System Verilog.
  • Must have experience in UVM.
  • Must have MIPI protocol knowledge.
  • Experience in any scripting language like perl / shell / python.
  • Experience random-constrained, coverage-driven techniques, functional coverage,  assertion based verification.
  • Knowledge in other protocols would be plus.

Required Skills:

  • System Verilog (SV), UVM, Any Scripts(Perl or shell or python ), Protocol –  MiPi

Experience: 6+ years

Work Location: South Korea

Package: Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]