Senior Verification Engineer / Project Lead – AMS Modelling 2014-04-17T14:25:27+00:00


  • 10+ years of experience in AMS modelling /  Analog Design and AMS modelling


  • B.E in Electronics / Electrical Engineering
  • M.Tech or PhD in Micro-electronics an advantage


Must Have

  • Strong industry experience with AMS modelling languages Verlog AMS or VHDL AMS is a must.
  • Good understanding of Advanced/Behavoiral modelling techniques for Analog cells in a Mixed Signal Design. (E.g. Real values modelling, wreal).
  • Develop models for at various  levels of abstraction  for Mixed Signal SoC Verification flow.
  • Good understanding of fundamentals of Analog concepts with experience in verifying complex Analog circuits.
  • Mixed Signal Spice Netlist simulation.
  • Exposure to scripting langauges.

Nice to have

  • Knowledge of Analog/Mixed Signal design concpets and exposure Analog/Mixed Signal design is an advantage.
  • Knowledge of e, Specman / System Verilog concepts is  an advantage.
  • Knowledge of Methodology based verification (eRM/UVM) is desirable.
  • Knowledge of SOC verification concepts, Digital design concepts.

Job Description

  • Responsibilities include developing AMS models with schematic entry or design document as reference. Should be independent in understanding design and developing models.
  • Develop Advanced models for Analog cells
  • Models for use in digital simulator with digital modules.
  • Models for use transistor level simulators.
  • Understanding of Analog circuits with only schematic entry as reference with little inputs from designer.
  • Identify potential System issues and develop model to be able to simulate design  accordingly.
  • Verify AMS models before delviery to digital and analog SOC verification teams.
  • Mixed Signal Spice netlist and/or RTL simulation.

How To Apply

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