Senior Verification Engineer – SystemC modeling with TLM2.02015-10-15T10:00:00+00:00

Skillset

Must have

  •  Strong experience and deep knowledge with C++, SystemCand TLM2.0
  •  Strong experience in use of SystemC for modelling and/or verification
  •  Experience using simulation and synthesis tools from Cadence, Mentor, or Synopsys
  •  Excellent written and verbal communication skills
  •  A desire to lead high quality technical training courses.

Nice to have

  • Strong experience and deep knowledge with one or more of the following languages:     SystemVerilog, e, Vera, C, C++
  • Strong digital hardware design and verification skills using VHDL or Verilog
  • Strong experience and deep knowledge with one or more of the following methodologies: UVM, OVM, eRM, VMM
  • Experience with one or more of the following languages: Tcl, Perl, Unix scripting
  • Experience in a customer‐facing role such as training, consultancy, or application engineering

Experience

Must have

  • 3 – 12  Years Of Experience
  • Performing feature extraction from a specification
  • Coverage closure
  • Experience in Specman and eRM

Nice to have

  • Experience in SOC  Block Level Verification

Job Description

Responsibilities

  • Develop Verification Plan and Verification Architecture
  • Develop Tests and Testbench
  • Implement Functional Coverage Points
  • Achieve 100% Functional Coverage
  • Develop Verification Plan Documentation and Capture Results of Execution

Location: Bangalore, India.

How To Apply

Send your CV to [email protected]