SoC Verification Engineer – JobCode: HWDMYS_24082017_01 2017-08-24T11:47:04+00:00

Job Description:

  • Working experience in SoC verification and integration activities including but not limited to testplan development, test writing, debug, integration and familiar with verification methodologies such as OVM, UVM or VMM
  • Pre-silicon functional verification w/ strong systemVerilog, OVM/UVMKnowledge and random-constrained, coverage-driven techniques
  • SOC Verification skillset inclusive of knowledge of Fuse Manager / Interrupt Manager/ Interconnect Bus protocols / SystemManager
  • Functional coverage – framework development, coverage regression and coverage analysis.
  • Assertion Based Verification – Development of framework, Assertions and Debug.
  • Tools – VCS / NCSim
  • Exposure to Version Control tools – preferably GIT.
  • Debug using Waveform, Trackers, Breakpoints .
  • Ability to understand the domain and module through specs and relate to the trackers/ waveforms
  • Knowledge and implementation skills on constraint random verification approach
  • Debugging expertize /know how on tyical error scenarios – such as NOA, XMRE(cross module reference) , hanging simulations ,scoreboard errors
  • Protocol Knowledge on any of the below areas would be a plus : SATA, PCIe, USB, Interfaces : I2C, SPI, UART

Experience: 1 to 3 Years

Positions: 2

Location:  Malaysia


  • Highly competitive to match experience and capability

How To Apply: Send your CV with Job Code to [email protected]

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.