As the Synthesis/STA Engineer of the MPSoC design team in Hyderabad, you’ll be responsible for owning the synthesis and timing closure for multiple complex blocks.
Essential Duties, Competencies & Responsibilities include, but not limited to:
- Hands on ownership of Synthesis / Constraints / STA / ECO flow
- Expert in running Block level and Chip level STA in MCMM, DMSA environments
- Must have worked on multiple timing closure and constraint development
- Well versed with AOCV, POCV, Noise fixing methodologies
- Must have worked on ECO implementation cycles – functional, timing
- Interacting with RTL/PD/DFT teams to resolve all implementation issues
- Participate in design reviews and design closure discussions
- Develop or enhance scripts for various design closure activities
- Good understanding of complete physical design flow.
- Must have gone through multiple tapeout cycles, revisions and ECOs
- Expertise with Synthesis, STA tools (like DC, Primetime) is a must
- Strong scripting skills using Perl, TCL, C-shell, Make and/or other scripting languages.
- Timing characterization and post silicon timing correlation experience a plus.
- Experience/ project work on critical path simulation, clock path simulation (jitter/duty cycle) with Spice a plus
- Experience with CDC, Constraint verification, lint checks is a plus
- Strong verbal and written communication skills.
- 3-10 Years
- Highly competitive to match experience and capability