Senior Subsystem/System Verification Engineers2014-10-15T12:25:34+00:00

Job Description:
Taking pre-verified IP and adding white (or glue) logic for use in system/subsystem. The requirement is to verify the white logic Verification environments

  • SV-UVM
  • Verilog and C for legacy test benches
  • Formal – writing and proving properties

Location: Global, TVS can obtain work visa where required.

Package

  • Highly competitive to match experience and capability

How To Apply

Send your CV to [email protected] with “reference 103” in the subject of the email