System Software Engineer – JobCode:SWDIND160218_02 2018-02-21T16:25:11+00:00

Careers

Job Title:

System Software Engineer

Job Code:

SWDIND160218_02

Job Description

This role will be a key team member in the silicon validation team from prototyping of Next Generation RTL through Post Silicon Validation, Bringup and Characterization. Candidate needs to have strong knowledge of ARM architecture and Linux Kernel/Application/Driver development. The role would involve working with hardware team to understand the hardware and writing user applications in Linux that exercises hardware.

Skills Required

  • Experience with Linux based validation tests, ranging from directed tests for specific SoC blocks and IO interfaces to OS based system tests
  • Experience with pre/post-silicon validation, debug, performance characterization
  • Working knowledge of PCIe drivers
  • Proficiency in C and Python/Perl
  • Experience in debugging processor and cache interactions is a plus
  • Experience with firmware or device driver programming is a plus
  • Familiarity with core sight infrastructure is a big plus
  • Familiarity in building embedded linux systems for different hardware.

Location

  • India/ onsite location

Experience

  • 8+ years

Package

  • Highly competitive to match experience and capability
We're hiring

Apply for this position

  • Accepted file types: doc, pdf.
  • This field is for validation purposes and should be left unchanged.

More Opportunities

View all Career Opportunities

Share this Job

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.