UVM ASIC Verification (ECC/Error Correction/AES security) Engineer 2016-09-27T05:35:03+00:00

Job Description:

You will be responsible for functional verification of high performance ECC and AES security IP core with modern verification technology, such as UVM. Responsibility includes understanding functionality of digital designs, developing test plans and components of verification environment, running regressions, debugging failures, measuring functional and code coverage and improving test cases to meet coverage goals. This candidate will work closely with IP design teams.


  • Minimum of 6 years of work experience in design verification.
  • Strong hands on experience in the latest verification methodologies System Verilog and UVM.
  • Familiar with constraint random based verification, functional coverage, code coverage and assertions.
  • Experience in building BFM and C++ models of various IP cores.
  • Work experience of IP performance verification.
  • Experience in developing automation flow and scripts with Perl, Makefile, Tcl

Location: Bay area

Experience: 6 years


  • Highly competitive to match experience and capability

How To Apply Send your CV to [email protected]

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.