You will be responsible for functional verification of high performance ECC and AES security IP core with modern verification technology, such as UVM. Responsibility includes understanding functionality of digital designs, developing test plans and components of verification environment, running regressions, debugging failures, measuring functional and code coverage and improving test cases to meet coverage goals. This candidate will work closely with IP design teams.
- Minimum of 6 years of work experience in design verification.
- Strong hands on experience in the latest verification methodologies System Verilog and UVM.
- Familiar with constraint random based verification, functional coverage, code coverage and assertions.
- Experience in building BFM and C++ models of various IP cores.
- Work experience of IP performance verification.
- Experience in developing automation flow and scripts with Perl, Makefile, Tcl
Location: Bay area
Experience: 6 years
- Highly competitive to match experience and capability
How To Apply Send your CV to [email protected]