Verification Engineer- Coherency – JobCode: HWVIND120418_29 2018-04-12T13:56:16+00:00

Careers

Job Title:

Verification Engineer- Coherency

Job Code:

HWVIND120418_29

Job Description

  • Be responsible for a participate in and lead CPU and Graphics Cache Sub-System function verification domain.
  • Be part of a team of designers and verification engineers, working closely with other team members to implement and verify the functionality of a given design element within the context of the block, chip and overall system as well as to design features for the next generation in RTL.
  • Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem solving attitude.
  • Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
  • Experience of working on Functional Verification, SoC Verification, Emulation
  • Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience
  • Must have good communication skills and the ability to work in a team environment.
  • Preferably having experience in architecture such as x86 or ARM domain based SOCs

Qualification

  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

Experience

  • 5+ years of experience in GPU/SOC/IP Verification

Open Positions

  • 4

Location

  • Hyderabad/ Bangalore

Package

  • Highly competitive to match experience and capability
We're hiring

Apply for this position

  • Accepted file types: doc, pdf.
  • This field is for validation purposes and should be left unchanged.

More Opportunities

View all Career Opportunities

Share this Job

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.