- The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
- The responsibility of the position involves comprehensive pre-silicon, post-silicon test planning, testbench development using the advanced verification methodology such as systemVerilog-OVM, systemVerilog-UVM, assertion development, formal verification (property checking).
- You will be responsible for developing testplan for functional , develop the scalable testbench using the HVLs, test case development, debugging, coverage model
development, coverage closure.
- You will be working with analog circuit design team, digital design team, analog
modeling, characterization team, SoC integration team to complete the successful PHY level verification, integration into SoC, post-silicon validation.
- SoC verification experience, RTL integration experience is added advantage.
- 8-10 years industry experience, with 5+ years of experience in digital and mixed signal circuit design verification
- Verification of high-speed parallel/serial IO interfaces such as D-PHY, M-PHY, SATA, Display Port, PCIe, USB2.0,USB3.0, HDMI -Test planning, problem solving, debug, adversarial testing.
- Strong working knowledge of HVLs: SystemVerilog, VERA/e-Specman, UVM, Assertions.
- Excellent communication and teamwork skills
- Extensive block/core level verification experience
- SoC verification env setup, driving the tapeout, RTL integration experience is added advantage.
- Please see minimum qualifications.
Education: Required: Bachelor’s, Computer Engineering and/or Computer Science and/or Electrical Engineering Preferred: Master’s, Computer Engineering and/or Computer Science and/or Electrical Engineering
Work Location: California – San Diego
Package: Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]