- Experience in HVL based verification with expertise in System Verilog & UVM
- Must have expert understanding functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, and writing assertions
- Excellent communication skills (both verbal and written).
Key skills: System Verilog, UVM, functional coverage, assertions
Location: Bay Area
Package: Highly competitive to match experience and capability
How To Apply: Send your CV with Job Code to [email protected]