Blu Wireless Technology is a UK-based company that develops silicon proven mmWave wireless baseband IP for advanced WiGig applications. The company is growing rapidly, acquiring key partners and licensing its IP across the world.
TVS recently completed SystemC-based UVM software testing for Blu Wireless Technology. During the project TVS tested and verified Blu Wireless Technology’s SystemC IP design which also led to stream lining of the design process and improved IP.
Following an initial specification period it was quickly agreed that the best approach would be to deploy a SystemC test bench that would be UVM-compliant with a TLM2.0 interface. The custom verification infrastructure was developed by TVS engineers in India, in close collaboration with Blu Wireless Technology during the entire testing and verification process.
This paper outlines the infrastructure that was developed and the deployment of that infrastructure to enact the constrained based random verification.
1. The UVM infrastructure
The first Infrastructure developed was the TVS C++ class library (named TVM) equivalent to the UVM class library. Tests can be compiled using the free gcc based compilers.
- TVS implemented a library of base methodology classes and functions in C++ (including factory constructs, agents, monitors, scoreboard, drivers and sequencers) enabling easy conversion from TVM->UVM or UVM->TVM.
- The TVM library mimicked UVM phases such as compile, build, run, check etc.
- The library includes base classes for Constraint driven randomization using CRAVE (see section 2 below).
- Functional coverage is enabled through a TVM Functional Coverage Library.
- Code Coverage is also possible through gcov & lcov tools.
Additional UVM similarities are detailed in the “UVM correspondence and compliance” section.
2. Infrastructure for Constraint Driven Random Verification
Constraint based random verification is enabled through use of external randomization library called CRAVE. The syntax of CRAVE has been designed to naturally fit with C++ and SystemC
- The CRAVE library allows users to set constraints in a manner similar to UVM & System Verilog.
- CRAVE allows inline constraints, which can be formulated and changed incrementally at run-time.
- CRAVE is freely available under the MIT license. CRAVE is available via public repositories at GitHub.
3. Coverage through TVS Functional Coverage Library & asureSIGNTM
TVS developed a Functional Coverage Library(FCL) to enable Coverage Driven Verification(CDV). This library can be used either with TVM or individually on C++ based environments. The main features of the FCL are:
- The functional coverage report is generated in xml format (using the “Tiny xml” library add-on). This format is compatible withTVS asureSIGNTMso that coverage can be viewed against requirements.
- The FCL supports: multiple cover groups in a single instance; conditional coverage; exclusion or Inclusion of cross bins (by specific cover bin scope or bin specific); transition Bins (one series of incrementing transition); auto bins (upto 16 bits); cross coverage (for up to 4 cover points)
4. UVM correspondence and compliance
The following features give a strong correspondence between TVM and UVM:
- Constructs for agents, monitors, drivers, sequencers and score board are available.
- TVS has ensured that the factory registration and overriding concepts of UVM methodology are retained.
- Randomization is controlled using constraints similar to UVM / System Verilog via CRAVE.
- Ability to raise and drop objections.
- The config_db mechanism similar to UVM areavailable.
- Dynamic casting using DCAST similar to System Verilog’s $cast.
- Support for time out mechanism as in UVM.
- Reporting severity similar to UVM (through the SystemC inbuilt support).
- Uses TLM ports (interface method class), similar to UVM.
The following System Verilog features are also supported:
- Verbosity control of debug messages.
- Fine process control ((like fork-join, fork-join none, fork-join_any , tracking process using process handle) (by using systemC’s library has inbuilt support).
- Interface class.
This enables a reuse in respect of Verilog and System Verilog.
- The TVM code is easy to port to UVM and Vice-Verse.
- TVM can be re-used to verify RTL or for co-simulation between RTL and SystemC.
5. A verification methodology for TVM
The above infrastructure meant that TVS was able to follow its standard verification flow:
- This starts with a feature extraction. For each block to be verified the interfaces and block functionality is analysed to identify the major features. These can then be reviewed with the client and entered into asureSIGNTM.
- The next step is to identify how to verify each feature. Each feature can be mapped to a wide variety of verification goals such as:
- functional coverage targets;
- checkers such as scoreboards and assertions;
- tests (constrained random with or without a seed, or directed);
- code coverage targets;
- properties to be proved via formal verification;
- software execution;
- silicon validation lab tests;
A many-to-many mapping between features and verification goals allows an efficient verification plan to be captured within asureSIGNTM. Again this can be reviewed between TVS and the client.
- A TVM test bench can now be developed and the verification goals mapped to test bench components within asureSIGNTM. For example:
- A functional coverage goal can be mapped to the TVM functional coverage points that implement them.
- A test can be mapped to the TVM test thatimplements that goal.
asureSIGNTM now contains the feature extraction, verification goals and test bench elements, and the mappings between them. As tests are run they automatically report their results to asureSIGNTMvia an API and the code and functional coverage results are collected and automatically fed to asureSIGNTMvia XML (as mentioned above). Thus as each regression is run asureSIGNTMautomatically records the results (and the version control tag) so that progress can be monitored.
6. Initial Deployment
The above methodology supported by TVM and asureSIGNTM has been applied to block verification at BluWireless Technology with the following initial results:
- Re-usable TVM agents were developed for the major internal buses.
- High rates of both functional and coverage were achieved on all blocks.
- 100% statement coverage on all blocks.
- TVS worked with BluWireless Technology to perform a structured feature extraction process which was then converted to a functional coverage model. TVS were then able to generate tests to hit 100% of the plan.
- Throughout the coverage closure process TVS sent regular reports to BluWireless to allow them to track progress (via the asureSIGNTM Verification management tool)
- 21 bugs were discovered.
7. Future TVM developments
The following TVM improvements have been identified:
- Call-backs are not implemented. For now, as it is pure C++ library, C++ call-backs can be used (Courtesy : tedfelix.com/software/C++-callbacks.html).
- TVS has a Virtual Sequencer based mechanism but it needs further improvement to make it more compatible with the p_sequencer /m_sequencer based methods in UVM.
- There is currently no UVM-RAL model.
- uvm_event, uvm_event_pool and message passing using these functions need to be added.
- The functional coverage library support needs to be extended.
- The SystemC assertion library needs to be tested.
The first Infrastructure developed was the TVS C++ class library (named TVM) equivalent to the UVM class library. Constraint based random verification was then enabled through the use of an external randomisation library called CRAVE. A Functional Coverage Library was also developed to enable Coverage Driven Verification (CDV). This library can be used either with TVM or individually on C++ based environments.
The application of the TVS methodology was successful. Constraint based random verification was enacted and high rates of detection were achieved quickly for both functional and code coverage (the latter enabled by freely available gcov and lcov). In addition, discovered bugs were shared through Bugzilla where they were tracked to resolution.
Ray McConnell, CTO of Blu Wireless, commented, “Working with TVS has enabled Blu Wireless to improve the quality of its outgoing IP through advanced verification techniques. Moreover, we have seen significant cost reduction through a license-free environment and offshore execution, which are key for a start-up like ourselves”.
The SystemC-UVM infrastructure developed by TVS is now available for use by TVS on other projects. The SystemC library to enable UVM verification to be performed using SystemC rather than System Verilog is freely available here: http://www.testandverification.com/events/freely-available-uvm-systemc-library-19-feb-2015/.
For further information, contact TVS at [email protected].