Improving IP quality using SystemC-based UVM

When T&VS client BluWireless first approached T&VS with a requirement to verify their SystemC design it was quickly agreed that the best approach would be to deploy a SystemC test bench. This was quickly followed by a decision to be UVM-compliant with a TLM2.0 interface.

The first Infrastructure developed was the T&VS C++ class library (named TVM) equivalent to the UVM class library.Constraint based random verification was then enabled through the use of an external randomization library called CRAVE. A Functional Coverage Library was also developed to enable Coverage Driven Verification (CDV). This library can be used either with TVM or individually on C++ based environments.

Ray McConnell, CTO of BluWireless, commented “Our main objective was to improve the quality of our outgoing IP. After discussions with verification experts T&VS, we agreed to start coverage driven constrained random verification of our key IP blocks. T&VS enabled this through development of a UVM environment in SystemC”.

The functional coverage report is generated in xml format (using the “Tiny xml” library add-on). This format is compatible with the T&VS asureSIGN to enable a Requirements Driven Verification strategy.Mike Bartley, CEO of T&VS, commented “T&VS has a well-defined verification strategy based on the IP requirements, feature extraction and a UVM test bench, supported by asureSIGNTM . The infrastructure developed has enabled this approach to be applied to BluWireless SystemC designs in a license free environment.

The infrastructure was developed by T&VS engineers in India and early results of applying the methodology have been encouraging. High rates have been achieved quickly for both functional and code coverage (the latter enabled by freely available gcov and lcov). Bugs have also been discovered and shared through Bugzilla where they are also tracked to resolution.

Ray McConnell added “Working with T&VS has enabled us to improve the quality of our outgoing IP through advanced verification techniques. Moreover, we have seen significant cost reduction through a license-free environment and offshore execution which is key for a start-up. Communication has not been an issue especially with regular progress meeting with a UK-based export.

The SystemC-UVM infrastructure developed by T&VS is now available for use by T&VS on other projects. For further information, contact T&VS at [email protected].

The Client Benefits

  • A license free verification environment.
  • Advanced verification techniques deployed based on T&VS Requirements Driven Verification strategy with a UVM compliant SystemC test bench.
  • Demonstrable improved IP quality through metrics such as functional and code coverage, and bug discovery rates.