T&VS delivers performance improvements for a complex memory subsystem block for a leading smartphone manufacturer

About the Client
The client is a leading smartphone manufacturer with a reputation for shipping some of the highest performance hardware in the industry.

Background
The client specializes in high-performance multicore SoCs. The client was developing an Advanced Memory Subsystem (AMS) with enhanced memory performance for bandwidth hungry blocks. T&VS was selected to develop a performance model of the memory subsystem and for exploration of the subsystems performance features.

The T&VS Solution
T&VS developed a SystemC model for the Advanced Memory Subsystem to enable design exploration for better performance. This activity involved developing abstract models focused on performance and fully configurable parameters for features such as memory read-write delays, FIFO read-write delays, Counter delays, Arbiter logic delays, state machine delays etc.

The T&VS solution provided file-based configurability thus allowing the client to insert various configuration delay values. The performance models could read the delay values and configure the various blocks and sub-blocks at run-time. These delay values were cycle based thus allowing performance investigation in terms of cycles.

It was required to verify that the AMS met the expected performance targets and so T&VS developed a test bench that checked the cycle timings under various scenarios.
T&VS introduced various efficiencies in the model development. For example, the model contained a large number of registers and a script was written to auto-generate the required SystemC code. Register functions (such as read, write, bitwise and part-select access) were abstracted into a library.

Observability was added to the model via a TLM2.0 debug interface that enabled the client to verify performance and functionality at key nodes in the model.

The Client Benefits

  • T&VS introduced an efficient methodology for performance modelling
  • The cycle-based performance model allowed detailed architectural exploration including configurability of delays
  • A register model with API and script re-usable on future projects
  • A LPDDR4 Model with TLM-2.0 DMI support including read-write latencies re-usable on future projects