Pactron HJPC is a leading provider of board level solutions to the semiconductor industry. Based on a qualification of T&VS’ well-proven verification capabilities, Pactron chose T&VS as the partner for the verification of a complex FPGA design for a financial application.
T&VS created a detailed verification plan listing out the strategy for feature list extraction, test bench specification, verification plan development and functional and code coverage. Once the plan was ratified by the customer, T&VS developed a System Verilog based Bus Functional Model (BFM). In addition, the verification environment was designed to support Interrupt generator BFM with constrained enumeration support for interrupt selection.
T&VS set up a team of 5 people within a week of RFP and was able to achieve the target of 100% functional coverage within just 2 months. T&VS’ verification strategy helped Pactron achieve cost savings of nearly 40% on functional verification.
Ram Chandrashekar, Technical Manager at Pactron, commented, “T&VS was able to put together a team of qualified verification engineers in short time frame and reused a lot of its existing verification collaterals to cut the overall development time by 30%.”
Ghuru Kumaravelu, Engineering Manager at Pactron, concluded, “We are very pleased with T&VS’ services and wouldn’t think twice about recommending T&VS to any of our customers.”