T&VS provides DFT Solution for Network SoC

Background

The customers serves across the spectrum of electronics applications with innovative semiconductor solutions by leveraging its vast array of technologies, design expertise and manufacturing strength.

When the customer urgently needed a team of engineers for DFT implementation and execution of its network SoC, they turned to T&VS for help. T&VS was chosen as the preferred vendor on the basis of its track record in executing managed services programs.

The T&VS Solution

T&VS initially analyzed the design and estimated the effort for DFT implementation of the SOC. As part of this program, T&VS also had to execute DFT DRC for Scan and implement compression. The stuck-at coverage target for the SoC was an aggressive 99.8%.

T&VS implemented a unified and modular test bench framework to cater to USB-PHY, PCIE-PHY and DDR PHY testing. The test environment was developed to test analog modules like PLLs, temperature sensors etc. The same environment could be reused to create vectors for tester also.

T&VS used a blended model for project execution wherein the team structure provided flexibility for both off-shore mentoring and onsite support. By providing DFT specialists for the duration of the project, T&VS reduced customer overheads involved in hiring expensive fulltime DFT resources. The T&VS DFT strategy reduced event based vector to cycle based vector conversion effort to nil. T&VS’ competitive pricing for the framework also enabled customer reduce overall development costs.

For further information, contact T&VS at  [email protected].

Benefits of T&VS Solutions

  • Reduced Customer Overheads.
  • Event based vector to Cycle based vector conversion effort was reduced to null.
  • Reduction in overall development costs.