Category Archives: Active Event

T&VS @ Mobile UX London (MUXL) Conference. 10th November – London, UK.


T&VS are delighted to be sponsoring this the third annual MUXL conference and will be on hand throughout the day to discuss the full range of User Experience Testing Services that the company has to offer as well as offering attendees an opportunity to have a FREE QA Assessment.

Mobile UX London combines expert speakers with compelling topics to deliver a day of focused opportunities for learning and networking through quality presentations and practical workshops.

The T&VS Free QA Assessment

A T&VS QA assessment is a FREE instant review of your testing process with a concise set of recommendations and next steps. Whatever the challenges you are facing, if you are responsible for testing and want a quick independent review of your approach and processes then get in touch immediately. Read more

MUXL Event Summary

  • Annual Mobile User Experience London Conference
  • 10 November, 2017
  • De Vere West One, 9-10 Portland Pl, Marylebone, London W1B 1PR
  • Event Website: https://mobileuxlondon.com/muxl2017

EuroSTAR 2017 Talk: Dealing With Testing Debt in an Agile World. 7th November, Copenhagen.

At this year’s 25th annual EuroSTAR conference on software Testing (Copenhagen, Nov 6-9) T&VS will be presenting the following talk:

Dealing With Testing Debt in an Agile World

Companies adopt agile practises in different ways and even more so in the way they incorporate testing in that adoption. The authors of this paper have studied a number of companies using agile practises (such as Google, Spotify, Facebook, Microsoft, Ericsson, Unity, and Panda Strike) in order to better understand the range of testing practices they employ and their advantages and disadvantages. This analysis has then been deployed to help other companies to improve their approach to testing as they also adopt an agile approach.

This paper will report on the main findings of the analysis and the main learnings from working with companies adopting agile and their choices in testing strategy. In particular, the paper will give practical advice on how to both avoid building up testing debt in agile environments and how to deal with technical debt once it has built up.

Presentation Details

EuroSTAR Event Summary

About the Speaker

Mike Bartley (CEO and Founder, Test and Verification Solutions) has been involved in software testing and hardware verification for over 25 years. He started his career in testing of military software and safety-related aerospace applications using formal mathematical methods before moving into testing of commercial software.

Since 1994 Mike has also been involved in the verification of complex hardware and software products going into sectors such as mobile phones, HDTVs, smart cards, avionics and automotive. In 2008 Mike established TVS (Test and Verification Solutions: www.testandverification.com) to offer specialist services and products in hardware verification and software testing. TVS has now grown to a global company of 170 engineers.

Mike gained a PhD in Mathematical Logic from Bristol University. He has since obtained an MSc in Software Engineering and an MBA through the Open University, and is currently studying for an MSc in Computer Security.

Real Value Modelling for Improving the Verification Performance

Due to increasing unpredictability and complexity of systems, circuit SPICE and Fast SPICE simulation cannot deliver verification closure on time. With the demand to have more functionality in today’s designs, the high performance SoC’s should further accommodate Analog and Mixed Signal (AMS) designs. This leads to growing necessity of methodology for accurate and fast verification of AMS designs.

Mallikarjuna Reddy from Test and Verification Solutions and Venkatramana rao from Mindlance Technologies, presented on how to improve the verification performance using real value modelling at the DVClub Europe Conference-“Verifying Analog and Physical Designs”, on 12 September 2017.

You can view the slides and presentations here

Presentation Slides and Recordings of DVClub Europe- “Verifying Analog and Physical Designs”, 12 September 2017 are available now!

T&VS organized a European DVClub on 12 September 2017 with a focus on “Verifying Analog and Physical Designs”. Speakers were from Cadence, ARM, and T&VS and the presentations are now available on the T&VS website

Find out Slides and Recordings here

DVCon Europe 2017 & Accellera’s SystemC Evolution Day. 16-18 October, Munich Germany.

The Design and Verification Conference (DVCon) Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits and is sponsored by Accellera Systems Initiative.

Mike Bartley
Founder & CEO, TVS

As a member of the DVCon Europe Technical Steering Committee I’m delighted to share some details of this year’s event, which includes the 2nd edition of Accellera’s “SystemC Evolution Day”.  This spinoff from DVCon Europe will take place on the 18th October at the Technical University of Munich.

DVCon Europe At-A-Glance

Highlights of the DVCon program include Keynotes on Monday from Mr. Horst Symanzik from Bosch Sensortech “Consumer MEMS Products: Quality rather than Commodity” and Mr. Berthold Hellenthal from Audi on Tuesday about “Driving Virtual Prototyping of Automotive Electronics.”

There are Panels on “The Best Tools for Driving Safety and Security in Automotive Applications” and “Intelligent Automation: How to Decide What to and What not to Automate?

For the first time, DVCon Europe will also feature a 5G special interest session, with industry experts from Intel, Nokia and Rohde&Schwarz, who will provide insights on the path to 5G, highlight Spectrum opportunities and challenges, and offer also a Test & Measurement perspective for the emerging next generation of cellular communication.

The DVCon keynotes, papers, presentations and panels unite the practical application of state-of-the-art design and verification techniques, applied to a broad mixture of different domains. Primary areas of this year’s program include System Level, Virtual Prototyping, Advanced Verification with UVM and Formal, Design for Functional Safety, IP Reuse, Mixed-Signal and Low Power Techniques.

SystemC Evolution Day 2017

The SystemC Evolution Day is a full-day technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. This is the second event after a successful first edition in May 2016.  In several in-depth sessions, current and future standardization topics around SystemC will be discussed in order to accelerate their progress for Accellera and IEEE standard’s inclusion.

  • Wednesday, October 18, 2017
  • Technical University of Munich
  • FREE to Attend (Registration Required)
  • Additional Information

 

AESIN 2017 – The Premier UK Auto Electronics Conference

At this year’s AESIN 2017 Conference (Automotive Electronic Systems Innovation Network) Dr. Mike Bartley, Founder and CEO of T&VS, presented the latest updates on the recently announced CAPRI Project – which brings together an experienced consortium of partners from industry, academia and local authorities to deliver a complete end to end POD (Pods on-demand) mobility service.

Download the Presentation

  • Presentation Agenda
    • About the CAPRI Project
    • Applying Hardware Verification Techniques in Software Testing?
      • Constrained random techniques
      • Functional Coverage
      • Assertion-based checking
    • Compliance to ISO26262
      • Requirements-Driven Test and Verification
        Shift-left

Presentation Abstract

The CAPRI consortium builds upon current research and development work within Connected and Autonomous Vehicles and will take this forward to specify the next generation of PODs capable of seamlessly transferring between the on-road and pedestrian environments and harnessing V2X connectivity.

The consortium aims to collate sufficient evidence from the deployment trials and simulation testing to support PODs becoming a recognised vehicle classification for use on public roads and so enable the next generation of PODs capable of safely travelling at on-road speeds on public roads.

The presentation at AESIN 2017 will first discuss two of the main technical objectives of the project:

  1. Verifying and validating the safety and security of the next generation of PODs for both the on and off road environment.
  2. Collating sufficient evidence to support PODs as a new vehicle classification.

The presentation will then go on to consider the solutions being investigated by the project, specifically:

  • Security solutions for the main POD use cases
  • Verification methodologies for the software deployed on the PODs in both simulation and physical test environments
  • Both of the above activities will be informed by a detailed accidentology at the start of the project

Presentation Schedule

  • AESIN 2017 – Tuesday, October 3, 2017.
  • National Motorcycle Museum next to Birmingham Airport
  • Talk: Verifying and Validating the Safety and Security of Connected and Autonomous Vehicles
    • Presented by Mike Bartley, CEO and Founder of T&VS
    • Tuesday, October 3, 2017 at 3:40pm
    • Track 2: Research and Development
  • Register for the Conference
  • Follow @UKAESIN and @testandverif on Twitter

About AESIN

The UK has strong credentials in the automotive sector from the University R&D base through to the seven volume car and eight commercial vehicle manufacturers. Times are changing and the race is on. The market winners in this race will be the automotive companies that engage in open innovation practices, developing new partnerships in a technology fuelled eco-system enabled by intelligent systems and connectivity. We are proud to introduce a dedicated UK initiative focused on the accelerated and advanced delivery of Electronic Systems into the car and infrastructure: Automotive Electronic Systems Innovation Network or ‘AESIN’.

The AESIN Conference 2017, builds on the success in previous years and is now being established as the premier UK Automotive Electronics Conference. This year the organisers expect an even bigger and better show with more than 200 delegates expected and capacity for over 20 exhibitors at the popular National Motorcycle Museum next to Birmingham Airport. Along with headline keynotes from Industry and updates from Government, there will be parallel technical tracks covering the six key workstream areas covered by AESIN which include:

  • ADAS & AV
  • Automotive Electronics Security
  • Connected Car
  • More Electric Powertrain
  • Research & Development
  • Software

Can Formal Verification Help Make Robotic Assistants Trustworthy?

Dr Clare Dixon from the University of Liverpool to present keynote address at Formal Verification 2017 – sharing her experiences from the EPSRC-funded Trustworthy Robot Assistants project

June 1st 2017,  Bristol, UK. – Test and Verification Solutions (T&VS) today announced details of the keynote presentation and the full program of technical presentations and panel discussion for Formal Verification 2017 (FV2017). Now in its Fifth successful year FV2017 is organised by T&VS and is Europe’s premier forum dedicated to discussing the application of Formal-based techniques to the verification and validation of complex SOCs, embedded hardware and software.

FV2017 is a one-day, free-to-attend conference that takes place in Reading, UK on Tuesday 27 June 2017. It is also available as a simulcast webinar.

“Once again, we have a very strong program and I’m especially pleased to have Dr Clare Dixon from the University of Liverpool join us to provide the keynote and to share her perspective on Robotic Assistants and what we need to do to ensure they are reliable, safe and trustworthy.” said Mike Bartley, CEO and Founder of T&VS. “Clare has over 20 years’ experience working in Formal and her award winner paper “The Fridge Door is Open” sets the scene for what we can expect.”

Keynote Details

Technical Presentations

Additional Information

For additional information and to register please visit:

http://www.testandverification.com/conferences/formal-verification-conference/fv2017/

FV2017 is free to attend and is made possible through the support of its sponsors: Cadence, Mentor, Onespin Solutions, Synopsys and T&VS.

About T&VS

T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.

T&VS Company Contact

 

 

See T&VS at DAC 2017 – 18-22 June, Austin TX.

The Design Automation Conference (DAC) is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and  intellectual property (IP). DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

At this year’s event Mike Bartley, founder and CEO of T&VS will be contributing to the following panel discussion.

DAC Panel : Verification Necessity: When is Enough Too Much?

Mike Bartley
T&VS Founder and CEO

One contributing factor to the growing verification complexity is the emergence of new layers of verification requirements that did not exist years ago and that are driving the need for new solutions and expertise. Given a complex SoC project’s constraints (i.e., finite resources, finite time, and finite budget) some of the important questions that will be put to the panel include: How do you construct an efficient, effective, and productive verification flow?  and When is a proposed verification solution a necessity or nicety?

  • Moderator: Brian BaileySemiconductor Engineering
  • Wednesday June 21, 4:30pm – 5:20pm –  12AB
  • Track: EDA and Embedded Systems
  • Panelists:
    • Mike Bartley – Test and Verification Solutions
    • David Lacey – Hewlett Packard Enterprise
    • Ashish Darbari – OneSpin Solutions GmbH, Munich, Germany
    • Lauro Rizzatti – Rizzatti LLC, Portland, OR
    • Amol Bhinge – NXP Semiconductors, Austin, TX
  • DAC Website: Verification Necessity: When is Enough Too Much?

Meet Us at DAC 2017

If you would like to meet up at DAC to discuss you Test and Verification requirements, including all aspects of Hardware Verification, Software Testing, Security Testing & Data Protection or Safety Compliance, please contact us to arrange a suitable time and place.