DVClub Blog

DVClub Europe, 8 September 2014 – Recordings and Presentations now Available!

The slides and presentation recordings from the last DVClub Europe (8 September 2014) are now available on the TVS Website.  They will be available until Wednesday, 24 September 2014, after which time you will need to register to our website. Do you have a story to tell and would like to share it at the next DVClub?  [...]

2014-09-17T10:37:16+00:00 17th September, 2014|Active Event, DVClub, Events|

DVClub Europe – Performance Modelling using SystemC & TLM 2.0

Join Venkatesh Vasudevan of  TVS at DVClub Europe on Monday, 8 September 2014, where he will present on using Approximately Timed (AT) Modelling for Performance Modelling of Designs. Venkatesh will explain the concepts and how they have been applied to performance modelling of System-on-Chip (SoC) blocks including LPDDR4 Memory Controller, AXI4 bus etc.  Custom phases have [...]

2015-07-15T15:02:53+00:00 5th September, 2014|Active Event, DVClub, Events, SystemC|

Last few days to register for DVClub Bangalore on 2 September ‘Maximizing Benefits of UVM’

Join us on Tuesday, 2 September 2014 for the DVClub Conference, where Dr.Mike Bartley, CEO and Founder of TVS presenting on ‘Primer on UVM 1.2’. This will be followed by Rambabu Maddali, Engineering Manager at Audience, who will present on ‘Challenges and Traps in UVM adoption’. Malathi Chikkanna, Member Technical Staff at AMD presenting on [...]

2014-09-11T09:40:20+00:00 28th August, 2014|Active Event, DVClub, Events|

DVClub Europe – Performance Verification

The next European DVClub takes place 8 September (11.30 BST) and will focus on performance verification.  With software development dominating modern SoC development schedule and cost, validating software in hardware context has become a centrepiece of SoC Design and Verification flow. Virtual prototyping solutions are revolutionising embedded platform-based designs by offering a tightly coupled HW/SW [...]

2014-09-11T09:30:09+00:00 26th August, 2014|Active Event, DVClub, Events|

“Challenges and Traps in UVM adoption” at DVClub, Bangalore on 2 September

At DVClub, Bangalore on 2 September, Rambabu Maddali from Audience Communications will present on “Challenges and Traps in UVM adoption”. If you are a verification professional working on UVM, you cannot afford to miss this presentation! This presentation will highlight System Verilog based Constrained Random Verification methodologies which have been talked about for the last [...]

2014-08-13T10:06:45+00:00 12th August, 2014|DVClub, Events, Upcoming Events|

Slides and Recordings Available for DVClub Europe – 7th July 2014

The Assertion Based Verification DVClub Europe took place on Monday, 7th July 2014 and was very well received, with presentations from ARM, Freescale Semiconductor, Mentor Graphics and Synopsys. If you would like to review the recordings of the presentations, they are now available on the TVS Website along with the slides.  They will be available to [...]

2014-09-11T09:27:50+00:00 11th July, 2014|DVClub, Events|

DVClub Shanghai DVClub – Presentations and Recordings Available

The second DVClub Shanghai event, Experience of ARM Based Design Verification, took place on Friday, 27th June and was very well received with presentations from Test and Verification Solutions Ltd, Mentor Graphics, Cadence, Verisilicon and AMD.  The presenter slides and recordings are now available on the TVS Website if you would like to review them. [...]

2014-08-05T11:21:59+00:00 8th July, 2014|DVClub, Events, TVS-China|

Automating Assertion Based Verification – DVClub Europe (July 7th 2014)

We would all like to see designers adding assertions to their code.  Unfortunately, the effort and time required by the designers to write these assertions often prevents them from creating the assertions.  The language knowledge and skills required to write assertions often adds a further barrier.  Mark Hanover (Mentor Graphics) presentation at the next European [...]

2014-08-05T11:28:32+00:00 25th June, 2014|DVClub, Events, Hardware Verification|

July DVClub – Assertions: A Smart Path to Low Power Verification of Complex SoCs

In the next DVClub Europe, Monday, 7th July, Gaurav Jain, Senior Design Engineer from Freescale Semiconductor, will present a case study on the deployment of System Verilog low power assertions along with CPF enabled dynamic simulations to verify a Next Generation Low Power SoC. and how multiple assertion categories were deployed to target verification of [...]

2014-08-05T11:31:03+00:00 18th June, 2014|DVClub, Events, Hardware Verification|
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