Category Archives: DVClub

What Are the Several Types of Software Security Testing?

Software security testing is a type of security testing that aims to reveal loopholes and weaknesses in the security mechanism of applications and systems. The prime objective of security testing initiatives is to determine whether an application’s data and resources are protected from potential intruders and if the application is vulnerable to common and sophisticated attacks. This article explores how several types of software testing can help organizations achieve security goals.

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Find how T&VS Security Testing Services help ensure the correct security features are built into devices at the outset and processes to assist with ongoing maintenance and updates.

DVClub Europe, 8 September 2014 – Recordings and Presentations now Available!

The slides and presentation recordings from the last DVClub Europe (8 September 2014) are now available on the TVS Website.  They will be available until Wednesday, 24 September 2014, after which time you will need to register to our website.

Do you have a story to tell and would like to share it at the next DVClub?  We are always looking for good end user case studies to share with the community.  Contact Mike Bartley for more information on how you can take part.

Thank you for your continued support and we look forward to seeing you again at the next event!!

DVClub Europe – Performance Modelling using SystemC & TLM 2.0

Join Venkatesh Vasudevan of  TVS at DVClub Europe on Monday, 8 September 2014, where he will present on using Approximately Timed (AT) Modelling for Performance Modelling of Designs. Venkatesh will explain the concepts and how they have been applied to performance modelling of System-on-Chip (SoC) blocks including LPDDR4 Memory Controller, AXI4 bus etc.  Custom phases have been introduced where applicable and the TLM 2.0 Generic Payload is used as much as possible.

You can reserve your place at one of our venues in Bristol, Grenoble and Sophia.  If you are unable to attend the DVClub in person, why not join by Remote Access.

Last few days to register for DVClub Bangalore on 2 September ‘Maximizing Benefits of UVM’

Join us on Tuesday, 2 September 2014 for the DVClub Conference, where Dr.Mike Bartley, CEO and Founder of TVS presenting on ‘Primer on UVM 1.2’. This will be followed by Rambabu Maddali, Engineering Manager at Audience, who will present on ‘Challenges and Traps in UVM adoption’. Malathi Chikkanna, Member Technical Staff at AMD presenting on ‘Best practices in UVM’ to develop a re-usable and scalable verification environment. You can attend the FREE event in person or access it remotely. Why not come along and experience excellent informative UVM presentations and networking opportunity

DVClub Europe – Performance Verification

The next European DVClub takes place 8 September (11.30 BST) and will focus on performance verification.  With software development dominating modern SoC development schedule and cost, validating software in hardware context has become a centrepiece of SoC Design and Verification flow.

Virtual prototyping solutions are revolutionising embedded platform-based designs by offering a tightly coupled HW/SW debug, functional verification and performance analysis capabilities.  Mark Carey of Mentor Graphics will illustrate the level of control, visibility and analysis capabilities available on a “pure” and “hybrid” virtual prototypes to meet the SoC functionality and performance goals.

Join us in person at various European locations or globally via remote access!  Additional information and registration can be found here!

“Challenges and Traps in UVM adoption” at DVClub, Bangalore on 2 September

At DVClub, Bangalore on 2 September, Rambabu Maddali from Audience Communications will present on “Challenges and Traps in UVM adoption”. If you are a verification professional working on UVM, you cannot afford to miss this presentation!

This presentation will highlight System Verilog based Constrained Random Verification methodologies which have been talked about for the last 9+ years.  However, only after UVM introduction, majority of the verification teams started to adopt the methodology in rapid manner.  This topic will also highlight the motivations for moving to UVM from existing Verilog based verification environments and the challenges/benefits of the migration process.

Plan now to join us at the event and do not miss this opportunity to network with fellow verification professionals. Registration is completely free and webinar registrations are open too.

Slides and Recordings Available for DVClub Europe – 7th July 2014

The Assertion Based Verification DVClub Europe took place on Monday, 7th July 2014 and was very well received, with presentations from ARM, Freescale Semiconductor, Mentor Graphics and Synopsys.

If you would like to review the recordings of the presentations, they are now available on the TVS Website along with the slides.  They will be available to you without having to log in until the 18th July, after this date you will need to register on our website.

The next DVClub will be discussing Performance Verification and will be taking place on Monday, 8th September 2014, why not register your interest at and be one of the first to secure your place!

Do you have a story to tell and would like to share it at the next DVClub? We are always looking for good end user case studies to share with the community.  Contact  Mike Bartley for more information on how you can take part.

DVClub Shanghai DVClub – Presentations and Recordings Available

The second DVClub Shanghai event, Experience of ARM Based Design Verification, took place on Friday, 27th June and was very well received with presentations from Test and Verification Solutions Ltd, Mentor Graphics, Cadence, Verisilicon and AMD.  The presenter slides and recordings are now available on the TVS Website if you would like to review them.

 

 

Automating Assertion Based Verification – DVClub Europe (July 7th 2014)

We would all like to see designers adding assertions to their code.  Unfortunately, the effort and time required by the designers to write these assertions often prevents them from creating the assertions.  The language knowledge and skills required to write assertions often adds a further barrier.  Mark Hanover (Mentor Graphics) presentation at the next European DVClub will explain a solution called Questa PropGen which automates ABV.   It enables the verification team to generate properties automatically using existing test environments and reduces the amount of manual coding of assertions.

Mark has been involved in the design and verification of complex SoC’s for over 15 years with positions in a number of commercial and mil-aero companies and will share his experience with us.

Why not register and join us at the next DVClub on 7th July?  We have venues throughout Europe and Remote Access and it’s a great opportunity to network!!!