Category Archives: Requirements

T&VS Contributes to PEnDAR Project

A Feasibility Study Into the Cost-Effective Capture, Validation and Verification of the Performance (and Resource Cost) of Complex Systems During the Design Process

PEnDAR (Performance ENsurance by Design, Analysing Requirements) is an InnovateUK funded collaborative project between Test and Verification Systems (T&VS), Predictable Network Solutions (Lead Participant), and Vodafone Group.

With society’s increasing dependence on Information and Communications Technology (ICT) the need for better means to predict and assure the performance of critical infrastructure grows.  Today, the performance of large-scale Cyber Physical Systems and System of Systems is often an unplanned emergent property that can vary substantially during operational lifetime.  Although this hazard is sometimes validated as part of system commissioning, it often finds its way into deployed systems, impinging on the systems usefulness as well as increasing the total lifetime cost.

The PEnDAR project is a study into the feasibility of systematically considering both performance and resource costs early in the system development lifecycle (SDLC). The goal is to consider how to enable the Validation & Verification of cost and performance in the field of distributed and hierarchical systems via sophisticated but easy-to-use tools.

It is thought likely that this approach will be applicable to both new and established systems and be able to support both initial and ongoing incremental development.

This feasibility study aims to investigate the technical issues involved in effectively incorporating the mature mathematical techniques already available to capture, validate and verify the performance (and resource cost) of such complex systems during the design process rather than as an emergent property from the design process.

T&VS Contribution

As part of this collaborative project T&VS investigated the following critical items and incorporated the results into the final project report.

  • The feasibility of integrating performance V&V into a safety standards-compliant process suitable for safety-critical applications such as automotive.
  • Extending existing standards-compliant requirement sign-off tools to manage the capture and decomposition of performance/resource V&V requirements into specifications, features and sign-off criteria.
  • How the performance V&V process can be incorporated into a standards-compliant workflow for safety-critical applications.
  • Assessed the potential savings of performance/resource V&V in automotive software development and the potential benefits of applying a similar methodology in the SoS integration market.

Deliverables – Slideshare & Recordings

The findings from the study are planned to be presented as a paper in a special issue of IEEE Design & Test.

Find Out More

If you would be interested in applying the lessons from this project to your business please contact one of our V&V consultants today.


Alternatively call one of our local sales offices.

 

Webinar: Managing Requirements and Verification with asureSIGN and asureVIEW — 17 Nov.

In this FREE online webinar you will learn how good verification management can help to:

  • “Shift Left” by defining verification tasks against requirements
  • Improve quality of requirements through process
  • Define a minimal test suite against requirements
  • Efficiently test of variants across multiple product lines
  • Automate verification reporting by tracing requirements to test execution
  • Manage multiple verification projects from a single dashboard
  • Provide requirements proof of implementation for compliance to safety standards, such as ISO26262 DO254/178, IEC61508, IEC 62304, etc.

Webinar Event Summary

  • Managing Requirements and Verification with asureSIGN and asureVIEW
  • November 17, 2015. — 15:30- 4:00pm
  • FREE Registration

Join T&VS at the NATEP Showcase 2015 – 12 Nov. Coventry, UK.

natepNATEP is a national programme under which aerospace supply chain companies are developing more than 100 new technologies for the UK and global aerospace industry.

The very first NATEP Showcase event will celebrate the success of a number of the participating companies and provide an opportunity for them to present their new technologies to the wider world. In addition to this, higher-tier and customer aerospace companies that are supporting NATEP projects will explain why companies ranging from Rolls-Royce, Airbus and AgustaWestland to UTC, Meggitt and Cobham are behind NATEP and are encouraging as many NATEP projects as they can.

T&VS at NATEP

natep-happen-smallAs one of the first recipients of a NATEP grant, T&VS will be at the event to talk about its asureSIGN requirements and verification management product and its extension to provide integrated support for the development of hardware, software and systems under avionics safety guidelines DO-254, DO-178B/C and ARP4754.

T&VS will also have a stand there where attendees can find out more about what T&VS and asureSIGN can offer in the aerospace sector.

It promises to a busy and informative new technology event with participating companies, potential customers and other aerospace industry stakeholders all in attendance.

Event summary

AESIN 2015 – Ensuring Automotive System Integrity through Advanced Software Verification

The rising tide of opportunities for electronics in the automotive brings with it various technical hurdles not the least of which is ensuring system integrity. Consider for example ADAS (Advanced Driver Assistance Systems) where the operating environments are so complex and so diverse that traditional approaches no longer scale.

aesin-2015b Continue reading

T&VS wins avionics verification project in China to DO-254 standard

PRESS RELEASE

Bristol, UK, 4th November 2014 – T&VS, a leader in software test and hardware verification solutions, today announced that it has won a significant verification service project in China. T&VS is working with its Chinese partner, TopBrain Design Systems, verifying a new avionics FPGA design in compliance with avionics standard DO-254.

The DO-254 standard is recognized by the Federal Avionics Administration (FAA) as a means of compliance for the design of complex electronic hardware in airborne systems. Such hardware includes FPGAs, PLDs and ASICs. The DO-254 standard is the counterpart to the well-established software standard RTCA DO-178B/EUROCAE ED-12B. With DO-254, the FAA recognises that avionics equipment contains both hardware and software, and each is critical to the safe operation of aircraft.

The verification project service by T&VS helps the leading company to verify its safety critical avionics FPGA designs. T&VS will be applying advanced verification techniques such as constrained random verification, functional verification and assertion-based verification to the project. As required by DO-254 requirements traceability will be applied and T&VS will use its unique asureSIGN technology to ensure that requirements can be traced to the verification data generated through the advanced verification techniques being applied.

Mike Bartley, CEO and founder of T&VS, commented, “This deal confirms the strength of our partnership with TopBrain. There is a strong demand for advanced verification expertise in China and with more than 130 skilled engineers globally, T&VS is well equipped to respond to those needs, and it makes perfect sense for T&VS to collaborate with TopBrain.”

Said TopBrain’s president Roger Lee, “This significant win is an important step forward for TopBrain as we look to capitalise on the strong growth that is occurring in the civil aviation industry in China. We appreciate this leading customer’s partnership and look forward to delivering an innovative, quality hardware verification solution that will enable them to get official process compliance certification for their leading project.”

Bartley added, “There are also a number of additional avionics products being designed in China that all require DO-254 compliance where T&VS has lots of expertise.”

T&VS and TopBrain are considering further DO254 projects in China and as part of its strategy in the country, T&VS plans to open an office there in 2015 to strengthen and underpin its presence in the region.

For information on TopBrain’s support and services for T&VS in China visit: www.topbrainds.com.

Further information on T&VS’ products and services is available at: www.testandverification.com.

About T&VS
T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.

About TopBrain
TopBrain Design Systems provides advanced verification solutions to customers developing complex electronics designs. TopBrain helps its customers to get advanced verification capability in a short time. TopBrain’s products and services include advanced hardware verification methodology service, tools, VIP, training courses, onsite/offshore supports to the local customers. In 2014 TopBrain became the official solution partner of T&VS in China.

T&VS Company Contact
Dr. Mike Bartley – T&VS
+44 7796 307958
[email protected]

TopBrain Company Contact
Roger Lee – TopBrain
+86 21 6630 6399
[email protected]

EE Times Blog: Moving Towards Requirements-Driven Verification & Test

ee-time-logo
In a recent blog for EETimes, Mike Bartley (founder and CEO of T&VS) emphasized the need for  Moving Towards Requirements-Driven Verification & Test.  A short abstract of the article is enclosed below. To read the full article visit EETimes.

mike-bartley-web
Due to the rising complexity, time-to-market demands, and variability involved in building requirements of critical hardware and software systems, it is absolutely essential to have a robust requirements sign-off capability. It’s particularly applicable for systems where the financial cost of failure is significant, when systems are safety-critical, or where there is a high security factor.

Our industry has moved from directed, to constrained random, to metric-driven — is RDVT the next step in its evolution?

Read the full article at EETimes.

T&VS to champion Requirements Driven Verification and Test at DVCon Europe

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PRESS RELEASE

Bristol, UK, 29 September 2014 – T&VS, a leader in software test and hardware verification solutions, today announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel. The company will be showcasing its driven verification and analogue mixed-signal (AMS) capabilities, together with other product developments.

DVCon Europe is a new conference for the application of software languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. DVCon has run successfully for over twenty years in Silicon Valley, so event organisers are expecting a great deal of interest in the first DVCon Europe.

At DVCon Europe, T&VS will be presenting two papers and one tutorial:

  • T&VS’s tutorial: ‘Requirements Driven Verification and Test (RDVT)’ will be on Tuesday October 14th at 11.30-13.00 and will outline what the development standards mandate and how they can be delivered through requirements-driven verification methodology.
  • T&VS’s first paper: ‘Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification’ will take place on Wednesday 15 October at 11.30-12 to be presented by T&VS’s Suresh Babu in partnership with Roman Wang of AMD.
  • T&VS’ second paper: ‘Requirements-Driven Verification Methodology (for Standards Compliance)’ will be held later the same day at 16.00-17.00 to be presented by T&VS’s Mike Bartley and Serrie Chapman.

On its DVCon Europe booth, Stand 1, T&VS will be showcasing its latest capabilities and product developments:

  • asureSIGN is a tool for managers, developers and integrators that ensures that product requirements have been successfully tested and implemented.
  • asureCOMPLY makes compliance easier with effective verification in the of safety standards compliance.
  • AMS VIP (Analogue Mixed-Signal Verification IP), offered as part of T&VS’
    asureVIP portfolio, is a suite of tools to provide an efficient, re-usable, development strategy that delivers verification, architecture IP, coverage collection and signoff of AMS designs.

Mike Bartley, CEO of T&VS and DVCon Chair, stated, “Visitors are invited to check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool and our analogue mixed-signal capabilities – or simply stop by for a chat.”

If you’d like to prearrange a meeting at the event please email Mike Bartley of T&VS at: [email protected]

About T&VS
T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.

T&VS Company Contact
Dr. Mike Bartley – T&VS
+44 7796 307958
[email protected]

Media Contact
Oliver Davies – Publitek Technology PR
+44 1225 470000
[email protected]

Visit us at DVCon Europe 2014

dvcon-europe-logoT&VS will be presenting a tutorial and exhibiting at this year’s DVCon in Europe, so if you’re visiting please check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool – or simply stop by for a chat.

The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits, more details below.

Read the blog article: “A European Twist to DVCon.”

 

What: DVCon Europe 2014
When: October 14-15
Where: Munich, Germany
Event Details: http://dvcon-europe.org
T&VS Stand Location: Stand #1, Strauss Foyer
T&VS Tutorial: Requirements-driven Verification Methodology for Standards Compliance

Requirements-driven verification is based on ensuring that feature-level requirements are adequately verified by tracing such requirements through to verification tasks. It is similar to Coverage-driven Verification from the sense that it is metric-driven but differs significantly because the metrics derive from requirements rather than verification goals

Requirements-driven verification is also required for compliance with the increasing number of standards that control development of hardware for domains such as automotive (ISO26262) and avionics (DO254). The tutorial will cover what the development standards mandate and how it can be delivered through requirements-driven verification methodology and will use an automotive example (lane crossing) to cover the three main issues regarding standards compliance and how they are covered through a requirements-driven verification methodology.

Read the Full Tutorial Details on the DVCon Europe website.

T&VS Talk #1: Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification

  • Wednesday, Oct 15, 11:30-12:30 [Session T2.4: Advanced Verification]
  • Presented by: Suresh Babu (Test and Verification Solutions) and Roman Wang (AMD)
T&VS Talk #2: Requirements-Driven Verification Methodology (for Standards Compliance)

  • Wednesday, Oct 15, 16:00-17:00 [Session T7.2: Verification Management]
  • Presented by: Serrie Chapman and Mike Bartley – Test and Verification Solutions
T&VS Talk #3: A Framework for AMS Verification IP development with SystemVerilog, UVM and Verilog AMS

  • Wednesday, Oct 15, 10:00-11:00 [Session T1.2: Analog / Mixed-Signal Design and Verification]
  • Presented by: Jeganath Gandhi Rajamohan, Mike Bartley – Test and Verification Solutions

About DVCon Europe

The Design and Verification Conference & Exhibition Europe is a new conference for the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.

For more information visit: http://dvcon-europe.org/conference/dvcon-europe-2014/

 

 

Janick Bergeron considers European Verification Challenges

We asked Janick Bergeron of Synopsys about the type of challenges Synopsys is currently seeing at user sites in Europe?

“Owing to Europe’s unique broad markets including automotive, communications, graphics, industrial and consumer SoC applications, the verification challenges are many and varied, and one size definitely does not fit all” replied Janick.

You can learn more about these challenges at Verification Futures /verification-futures

Janick added “However, recent developments for verifying very large SoC designs at leading edge process nodes are also applicable to designs in those other application spaces. These developments can only succeed after a large-scale R&D investment across many new technologies in partnership with industry leaders to accelerate innovation.”  Janick Bergeron.

Hear more from Janick about the solutions from Synopsys and other major EDA vendors at verification Futures.