Category Archives: RISC-V

5th RISC-V Workshop Proceedings Now Available

The Proceedings of the 5th RISC-V Workshop, hosted at Google’s Quad campus in California in November, 2016 are now available from:

The goal of the workshop was to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe and build consensus on the future evolution of the instruction set.

Each workshop helped document the rapidly rising popularity of RISC-V and the event was covered by a number of influential journals, including:

  • EETimes’ Rick Merritt
  • lowRISC’s Alex Bradbury live blogged Day 1 and Day 2;
  • Cadence’s Paul McLellan with his Breakfast Bytes blog
  • AB Open’s Gareth Halfacree with his Community Round-Up blog.

Links to these articles can be found at:

The 6th RISC-V Workshop

The 6th RISC-V Workshop will be hosted by NVIDIA and Shanghai Jiao Yong University in Shanghai China, May 9th-10th, 2016.

T&VS RISC-V Test and Verification Services

To help you deliver successful RISC-V based designs T&VS can offer specific services that build on and extend the world-class test and verification services that we have been delivering to the semiconductor industry since 2008.  Find out more.

Linley Microprocessor Report features on RISC-V ISA

risc-v-bannerThe RISC-V ISA has been featured in the latest edition of the Microprocessor Report in and item “RISC-V OFFERS SIMPLE, MODULAR ISA” written by David Kanter of The Linley Group.

Concluding Summary

On the basis of early developments, the RISC-V ISA appears promising. It offers all the basic RISC features witha few twists that simplify the implementation, thereby reducing die area and potentially power consumption. Compared with today’s two most popular ISAs, RISC-V offers considerable area savings, particularly for low end designs and the ability to add custom extensions. Compared with ISAs such as ARC and Tensilica, RISC-V offers fewer technical advantages but its open source business model will continue to drive interest in the new ISA.

Download the Report

The RISC-V Foundation has retained distribution rights for this report and the full report can be downloaded and freely distributed from their website at:

T&VS RISC-V Test and Verification Services

To help you deliver successful RISC-V based designs T&VS can offer specific services that build on and extend the world-class test and verification services that we have been delivering to the semiconductor industry since 2008.  Find out more.

 

T&VS extends CPU Verification Capability

PRESS RELEASE

Bristol, UK, 14th April 2015T&VS, a leader in software test and hardware verification solutions,today announced an extension of its CPU verification capability.

T&VS provides expertise to help companies ensure their hardware and software based products are reliable, safe and secure. At the heart of most products is a CPU core which will implement a variety of complex performance enhancements such as pipelines, multiple instruction issue, out-or-order execution, and branch prediction as well as the usual memory access acceleration such as caching.

These enhancements can break the functional correctness of the core and so require specialist verification techniques including constrained random instruction stream execution. Using this technique small assembler programs are generated for execution on the core. Verification expertise and tools are required to generate programs which verify the corner cases created by those complex performance enhancements.

T&VS has historically had expertise in CPU verification both advising and supporting a number of companies on their CPU verification strategies and execution. T&VS has now extended this capability with the development of a new Instruction Stream Generation tool (asureISG) and a new team of CPU verification engineers delivering CPU verification services.

Mike Bartley, CEO of T&VS, commented “I am very excited about this announcement. CPU cores are increasingly complex to verify and T&VS are now able to better support our clients by adding tools and execution resources to our existing CPU verification strategy services.”

The T&VS asureISG tool will initially support single CPU core verification but will soon be enhanced with multicore support. The semiconductor industry now uses multiple cores to add performance to SoCs and products and those cores often shares resources such as caches. Hence the need for multiple instruction streams that are generated by a tool that understands the potential bugs in the management of those shared resources.

Further information on T&VS’s products and services is available at www.testandverification.com.

About T&VS

T&VS (Test and Verification Solutions Ltd) provides expertise to help companies ensure their hardware and software based products are reliable, safe and secure..  Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes.  T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing.  T&VS’ hardware verification services include onsite/offshore verification support and training in advanced verification methodologies.  T&VS also offers Verification IPs, its own Verification (EDA) signoff tool and a CPU verification tool asureISG.

T&VS Company Contact
Dr. Mike Bartley – T&VS
+44 7796 307958
[email protected]