Category Archives: TVS-France

July DVClub – An Efficient Methodology to Find Bugs with ABV

The next DVClub will be taking place on Monday, 7th July with locations in Bristol, Cambridge, Eindhoven, Grenoble, Sophia Antipolis and by Remote Access.  Laurent Arditi a Principal Engineer at ARM France will be joining the Sophia Antipolis venue to talk about ‘An Efficient Methodology to Find Bugs with ABV (Assertion Based Verification)’.

This presentation will cover how ABV is an important part of functional verification and will demonstrate how they have successfully applied ABV on different generations and classes of ARM microprocessor designs and will help managers and engineers understand how to apply ABV for good results by showing examples on recent CPUs developed by ARM to illustrate, and to “prove” ABV has a high RoI.

To find out more about Laurent and the other speakers visit the T&VS website and register for your place on the July DVClub.

July DVClub on “Assertion Based Verification” – Call for Papers

Our next DVClub will be held on Monday, 7th July 2014 and would like to invite you to share a story which would be relevant to the topic of Assertion Based Verification.  The DVClub takes place across Europe with venues in Bristol, Cambridge, Eindhoven, Grenoble and Sophia and with Remote Access available, reaches around the world.  We are always looking for good end user case studies to share with the community.

For more information on how to take part in the DVClub or to submit your story, contact Mike Barley using the Contact Us Form.

Verification Qualification DVClub Slides now Available

The April DVClub on Verification Qualification was another successful event with talks from Synopsys, Infineon, OneSpin Solutions, Dialog Semiconductors and Cray Ltd.  If you were unable to attend, or if you did and would like to review the slides, they are now available on the TVS website without having to log in, after 5th May you will have to be registered on the website to view the slides or recordings.

The next DVClub will be discussing Assertion Based Verification and will be taking place on Monday, 7th July 2014 why not register your interest and be one of the first to secure your place!

Do you have a story to tell that is relevant to Assertion Based Verification and would like to share it at the next DVClub? We are always looking for good end user case studies to share with the community.  Contact Mike Bartley for more information on how you can be a part of the next DVClub.

We look forward to seeing you at the next event!!!

Last Chance to Register for Verification Qualification at April DVClub

The next DVClub will take place on Monday, 28th April 2014 in Bristol, Cambridge, Grenoble, Sophia and if you are unable to attend in person you can register for Remote Access.  The topic under discussion is Verification Qualification and with speakers from Synopsys, Infineon, Dialog Semiconductors, OneSpin Solutions and Cray Ltd it promises to be an interesting session.  Don’t miss this opportunity and register your place today.

DVClub – C/C++ Verification Effectiveness

The next DVClub is taking place on Monday, 28th April 2014 where Jean-Marc Forey of Synopsys will be talking about C/C++ Verification Effectiveness and how it is now pervasive in design conception, either through models at different stages of the design creation or by being embedded as firmware in the design itself.  If you have a bug escaping up to production, this can lead to high costs and delays in reaching the market, making it mandatory to assess and improve the effectiveness of the verification of the C/C++ code.  Certitude has been extended from its initial RTL focus to allow users to identify verification issues early in the design cycle.

To listen to Jean-Marc and the other interesting speakers we have lined up, register for one of the venues:  Bristol, Cambridge, Eindhoven, Grenoble and Sophia.  If you are unable to attend one of the venues, you can register via Remote Access.

DVClub – Measuring the Effectiveness of Verification Environments

Join us for DVClub on Monday 28th April, where Yogish Sekhar from Dialog Semiconductors, will be discussing Measuring the Effectiveness of Verification Environments.  During the presentation he will be talking about shrinking transistor sizes which mean more complex design is squeezed into the same area that was used a product generation earlier.  The world is aware of Moore’s law for design; but it is more applicable to the verification space today as verification complexity has increased exponentially.  There are multitudes of tools (i.e. simulators, methodologies) that tell us how we need to verify our designs and various different metrics that tell us what we have verified.  To listen to Yogish and the other speakers, register to attend at Bristol, Cambridge, Eindhoven, Grenoble, Sophia or by Remote Access if you are unable to attend in person.

DVClub 28th April – Certitude Tooling

Join us for the next DVClub on Monday, 28th April where Satwinder Singh of Infineon will be talking about using the Certitude Tool, to ensure the quality of a reusable testbench does not deteriorate across projects.  The flow described in this presentation reuses Certitude results to ensure that adding functionality for reuse doesn’t affect the testbench’s existing functions, in a run that takes about one hour (in contrast to a standard Certitude run taking about 3 weeks), enabling checks to be run more frequently. Register for your place to find out more.

DVClub – How do you Verify your Verification?

How do you know that the verification you have performed is sufficient?  We have long used coverage (functional and code) for stimulus feedback but this has a number of issues:

  • There are only subjective ways to measure the quality of the functional model
  • It is VERY easy to reach 100% code coverage and still have numerous bugs in the design (e.g. missing functionality)

When it comes to checkers there is no real way to measure quality or effectiveness unless you turn to “mutation testing”.  Under this technique bugs are deliberately inserted into the design to see if the verification can find them all.  The technique has been automated through tool support which generates metrics relating to quality of both stimulus and checkers (for both static and dynamic verification approaches)

In the next DVClub which will be held on Monday, 28thApril 2014 in Bristol, Cambridge, Eindhoven, Grenoble, Sophia and by Remote Access, we will look at both the technology and the tools available for verifying your verification.  The majority of the time will be spent looking at real user experience of applying the technology.  There will also be a presentation from a user who has developed his own tool for automating this approach.Register your place today!

DVClub Europe 28th April 2014

TVS is hosting the next DVClub on ‘Verification Qualification’ at various locations in Europe. This follows the highly successful DVClub on Managing Verification Data UCIS that took place on Monday, 13th January 2014 and was one of the most attended DVClub to date with almost 200 registrations.

The event will be held between 12:00 to 14:00 UK time at Bristol, Cambridge, Eindhoven, Grenoble and Sophia with remote access facility also being available. The confirmed list of presenters includes Infineon, Intel, ARM and ST among others. Register now.

 

Watch Five Talks on Using UCIS from DVClub Europe

Last Week’s DVClub on Managing Verification Data UCIS was one of the most successful to date with almost 200 registrations.  If you missed the event or if you would like to remind yourself of what was discussed on the day, the slides and video presentations are now available on the TVS website .  Don’t miss the next DVClub on Monday, 7th April 2014  where we will be discussing Test Bench Qualification.