Engineers can achieve a tremendous jump in verification productivity by tapping into VIP when architecting SoCs, implementing their blocks, and performing system integration. But to realize that productivity boost, engineers and tool managers need to carefully evaluate the VIP offering from the principal vendors to avoid the false economy that accompanies VIP of poor quality and dubious capability.
Success stories are what they are. The ones that catch your attention are backed up with user experience. So, two of the three ARM AMB verification IP examples that Cadence Design Systems has announced may merit your further investigation. They involve Hisilicon and CEVA.
More information available here.
To help our customers evaluate the quality of the T&VS VIP solutions we are pleased to make the following unit-level code samples and documentation available as a VIP Evaluation Package. You can view the package features here.
For more information, please visit the VIP page.
T&VS helped a leading smartphone manufacturer with the verification of its MPHY Anlaog IP. The scope of the activity was to model a MIPI MPHY analog IP using Verilog-AMS with real and to verify the model using a UVM-MS based testbench environment.
For more information visit here.
T&VS releases one of the first C- PHY UVM VIP which has extensive constrained random stimuli generation capabilities, configurable monitors and checks to ensure protocol compliance to MIPI standard for C-PHY specification 1.0.
Pre-defined coverage bins enable easier extension and coverage collection. The VIP has been verified for protocol compliance with asureSign-T&VS’ in-house Requirements tracking tool.
For information, please visit here or contact us at [email protected]
Bristol, UK, 29 September 2014 – T&VS, a leader in software test and hardware verification solutions, today announced that is presenting and exhibiting at the inaugural Design & Verification Conference and Exhibition Europe (DVCon Europe) to be held in Munich on 14-15 October 2014 at the Hilton City hotel. The company will be showcasing its driven verification and analogue mixed-signal (AMS) capabilities, together with other product developments.
DVCon Europe is a new conference for the application of software languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. DVCon has run successfully for over twenty years in Silicon Valley, so event organisers are expecting a great deal of interest in the first DVCon Europe.
At DVCon Europe, T&VS will be presenting two papers and one tutorial:
- T&VS’s tutorial: ‘Requirements Driven Verification and Test (RDVT)’ will be on Tuesday October 14th at 11.30-13.00 and will outline what the development standards mandate and how they can be delivered through requirements-driven verification methodology.
- T&VS’s first paper: ‘Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification’ will take place on Wednesday 15 October at 11.30-12 to be presented by T&VS’s Suresh Babu in partnership with Roman Wang of AMD.
- T&VS’ second paper: ‘Requirements-Driven Verification Methodology (for Standards Compliance)’ will be held later the same day at 16.00-17.00 to be presented by T&VS’s Mike Bartley and Serrie Chapman.
On its DVCon Europe booth, Stand 1, T&VS will be showcasing its latest capabilities and product developments:
- asureSIGN is a tool for managers, developers and integrators that ensures that product requirements have been successfully tested and implemented.
- asureCOMPLY makes compliance easier with effective verification in the of safety standards compliance.
- AMS VIP (Analogue Mixed-Signal Verification IP), offered as part of T&VS’
asureVIP portfolio, is a suite of tools to provide an efficient, re-usable, development strategy that delivers verification, architecture IP, coverage collection and signoff of AMS designs.
Mike Bartley, CEO of T&VS and DVCon Chair, stated, “Visitors are invited to check out our tutorial and technical talks or come along to our stand for the latest solution demos and announcements; including asureSIGN, our leading-edge leading Requirements Driven Verification tool and our analogue mixed-signal capabilities – or simply stop by for a chat.”
If you’d like to prearrange a meeting at the event please email Mike Bartley of T&VS at: [email protected]
T&VS (Test and Verification Solutions Ltd) provides services and products to organisations developing complex products in the microelectronics and embedded systems industries. Such organisations use T&VS to verify their hardware and software products, employ industry best practice and manage peaks in development and testing programmes. T&VS’ embedded software testing services includes onsite/offshore testing support including assistance with safety certification and security testing. T&VS hardware verification services include onsite/offshore verification support and training in advanced verification methodologies. T&VS also offers Verification IPs and its own Verification (EDA) signoff tool.
T&VS Company Contact
Dr. Mike Bartley – T&VS
+44 7796 307958
Oliver Davies – Publitek Technology PR
+44 1225 470000
Bristol, UK, 23 September 2014 –T&VS, a leader in software test and hardware verification solutions, today announced that it has joined the MIPI Alliance, which develops interface specifications for mobile and mobile-influenced industries. The move reflects the demand for T&VS’ Verification IP, especially in the mobile application sector that is moving quickly and thus creating new opportunities for the company.
Test and Verification Solutions (T&VS) has announced that it has expanded its asureVIP™ library of verification IP to cover protocols in MIPI, Memories, Universal Serial IO and Communication as well as a bespoke VIP development service.
The T&VS VIP offers many advantages to the user such as access to the source code, flexible licensing agreements and protocol compliance test suites. The latter enables the engineer to more quickly demonstrate that their design complies with the standard. The tests are mapped to the protocol specification so that the user can quickly see the intention of the test. Additionally the asureVIP™ library contains traffic generators which allows the chip integrator to quickly generate traffic across the interface. Synthesisable drivers and C interfaces allow the VIP to be used in emulation using SCEMI.
The UVM compliant asureVIP™ is written in native System Verilog so that debug becomes much easier given that the user has access to the code. Mike Bartley, Chief Executive Officer, Test and Verification Solutions said, “We have been working with clients on our VIP for some time now and a lot of the VIP is proven in a number of different environments and in silicon. Research suggests that companies are expanding their use of external VIP and adoption of UVM so I expect our UVM-compliant VIP to be very popular.”
The asureVIP™ library also contains eRM compliant VIP and in addition T&VS is able to VIP on demand under flexible ownership arrangements. The T&VS agile development process also means that the VIP is delivered in a number of short “sprints” allowing the client to make an early start on their verification.
For full details of the protocols available in the asureVIP™ library then please go our VIP page.
Read about the white paper here
Below is the pdf related to USB OVM Verification IP.