Jeganath Gandhi Rajamohan (Project Lead, Test and Verification Solutions) 2014-07-22T11:07:54+00:00

Title: Practical Verification of AMS SoCs

Abstract: Analog/Mixed-Signal Designs present us with verification challenges, even in this world of advanced verification tools and methodologies.  One of the main challenges is the simulation time; transistor level simulation would be ideal but would take days to simulate a simple power up of mixed-signal SOC.  With the number of functionalities per device ever increasing, it is impractical to simulate all scenarios with the transistor level simulation of the complete design.

One efficient strategy is to use pure digital methodology for full-chip with behavioural models for analog blocks to verify the analog/digital interface, complete digital features and analog/digital architecture of complete design.  While the analog design evolves, its behavioural model can be developed much earlier in the design phase along with the digital design, thus identifying any architectural flaws.  In parallel, spice simulation at module level can verify individual analog blocks.

Results from Module level spice netlist simulation for analog blocks can be used to validate the models.  The key verification targets are complete digital functions, analog/digital interface verification, and basic analog features.  The level of analog feature verification depends on accuracy of analog model but there will be a compromise between, accuracy and simulation performance, efficiency.  In addition to this flow, transistor level simulation of complete chip, where few modules are replaced with C models in a fast spice simulator can be used.  This could support the interface verification with the transistor level simulation.  These topics are discussed in this paper.

Biography: Jeganath has over 6 years of experience in Verification with both e and System Verilog . After completing his studies (a masters in Communication systems at Anna University, Chennai and a Post Graduate Diploma in VLSI design at Vedant, SCL, Mohali) he began his professional career as an Analog Mixed Signal ASIC verification engineer with Wipro Technologies, Pune. Working for the client, Texas Instruments in France, he has over 4 years of experience in AMS verification of Power management and Audio Control devices covering AMS model development, RTL/GLS verification with eRM based Verification environments and Full chip verification with the Fast Nanosim simulator. Later when he moved to Mindspeed Technologies, he was involved in VMM based verification environment bring up for Large Analog Mixed Signal Cross-point Switches. Jeganath is now working for TVS working for clients in Europe on both eRM based verification environment bring up for block level and SOC verifications while actively involved with guiding the TVS team across various locations with his experience in AMS verification.

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