Mathieu Behaghel (ST Ericsson) 2014-07-22T11:07:39+00:00

Title: Digital to Mixed-Signal Verification of Power Management SOCs Using Questa-ADMS

Abstract:  AMS and RF designs done in STEricsson have big analog functionalities and a lot of interaction between analog and digital functionalities. The partitioning of these designs makes them particularly difficult to verify. The most accurate solution would be to simulate the complete design with a spice simulator, however, increasing time to market constraints and circuit complexity make this approach impossible.

As STEricsson is a platform company, models have to be compatible with pure digital tools to simulate all the SOCs platform together.

As a consequence, we decided to use a digital centric methodology with real numbers to model the analog functionality.

This presentation will show how we developed the models to verify most of the design connectivity and functionality using the speed of digital simulators. It will then describe how Questa-ADMS was used to cover the electrical behaviour of the design by reusing the digital on top environment. Examples will be taken from a power management SOC.

Click here to download the presentation slides.

Video of the presentation

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.