|Designation:||CEO and Founder|
|Title:||Performance Modeling using SystemC & TLM 2.0|
Approximately Timed (AT) Modeling can be used for Performance Modeling of Designs. AT is an abstraction level where timing points are introduced and are represented by phases. The TLM 2.0 standard defines three schemes in general. These are single phase, two phase and four phase. These schemes can be extended by definition of custom phases.
T&VS has been involved in performance modeling of System-on-Chip (SoC) blocks. Models are being developed for blocks such as LPDDR4 Memory Controller, AXI4 bus etc. Custom phases have been introduced where applicable and the TLM 2.0 Generic Payload is used as much as possible.
Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.
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