|Title:||Case Study: Cutting performance verification time with automated characterization tests and analysis tools|
Abstract: Based on a state-of-the-art mobile ARMv8 compute sub-system case study, we will present an automated approach to exploring the performance envelope of the SoC interconnect and memory infrastructure. Balancing performance against DDR component and speed choices gets a substantial head start when you have all the fundamental performance metrics automatically extracted and presented for analysis with the push of a button. Biography: Nick Heaton is an ASIC and EDA veteran with more than 30 years of experience in the design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honours in Engineering and Management Systems, initially working as an ASIC designer for ICL in Bracknell. In 1993, he founded specialist ASIC Design and Verification Company Excel Consultants, servicing customers such as ARM® and Altera. In 2002, Nick joined Verisity (now Cadence) as Manager of Northern European Consulting Engineering. Nick currently works in the Cadence Research & Development organization as a Distinguished Engineer with special responsibility for Interconnect Workbench.
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