|Designation:||Senior Verification Engineer – Test and Verification Solutions|
Abstract: The SystemVerilog UVM based UVCs can be reused in the Specman-E environment. This eliminates the recreating the same environment in Specman-E, thus reducing the time and errors in redesigning the UVC. Mixed language utilities helps in configuration and stimulus generation from the existing SV UVC.
This paper shows how the SV UVCs can be reused in the Specman-E environment. It also explains data can be exchanged across the language and how checkers and coverage tasks can be reused.
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