DVClub China – Friday, 5 December 2014

Leverage Verification Acceleration for Verification Simulation

Friday, 5 December 2014
14:00 to 17:30 CST

Agenda

14.00 Arrival and Networking
14.10 Welcome
14.20 Test and Verification Solutions @ India, Bharath MP (Verification Engineer)
Title: Advantages of SCEMI Based BFMs
Presentation Language: English
14.50 Dynalith @ Korea, Dr Ando Ki  ( R & D Director)
Title: FPGA-based Transaction-level Verification Through de facto Standard Interfaces
Presentation Language: English
15.20 Coffee Break (10 minutes)
15.30 Cadence @ China, Harris Zhu (Principal Solutions Engineer)
Title: Guidelines to Accelerate UVM-based Simulations to Achieve Highest Levels of Acceleration
Presentation Language: Chinese
16.00 Mentor @ China, Justin Zhang (MED Technical Manager)
Title: UVM Acceleration, the Most Efficient way to Shorten your Verification Cycle
Presentation Language: Chinese
16.30 Atrenta @ China, Rui Wang (Lead Product Engineer)
Title: Speed up Emulation Debugging Using White-box Assertions
Presentation Language: Chinese
17.00 Local Q&A Session (5 minutes)
17.30 Close and Networking

Event Sponsors

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