DVClub China – Friday, 5 December 2014 2014-12-05T07:51:29+00:00

Leverage Verification Acceleration for Verification Simulation

Friday, 5 December 2014
14:00 to 17:30 CST

Agenda

14.00 Arrival and Networking
14.10 Welcome
14.20 Test and Verification Solutions @ India, Bharath MP (Verification Engineer)
Title: Advantages of SCEMI Based BFMs
Presentation Language: English
14.50 Dynalith @ Korea, Dr Ando Ki  ( R & D Director)
Title: FPGA-based Transaction-level Verification Through de facto Standard Interfaces
Presentation Language: English
15.20 Coffee Break (10 minutes)
15.30 Cadence @ China, Harris Zhu (Principal Solutions Engineer)
Title: Guidelines to Accelerate UVM-based Simulations to Achieve Highest Levels of Acceleration
Presentation Language: Chinese
16.00 Mentor @ China, Justin Zhang (MED Technical Manager)
Title: UVM Acceleration, the Most Efficient way to Shorten your Verification Cycle
Presentation Language: Chinese
16.30 Atrenta @ China, Rui Wang (Lead Product Engineer)
Title: Speed up Emulation Debugging Using White-box Assertions
Presentation Language: Chinese
17.00 Local Q&A Session (5 minutes)
17.30 Close and Networking

Event Sponsors

DVClub-Shangahi-v6

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.