Harris Zhu, Cadence 2014-12-26T07:46:14+00:00
Speaker:Harris Zhu, Principal Verification Acceleration Solutions Engineer
Presentation Title:Guidelines to accelerate UVM-based simulations to achieve highest levels of acceleration
AbstractIn a typical UVM based verification environment, a testbench contains a collection of verification components, both drivers and monitors that support interactions with various interfaces on a design. Additionally, there may be sequencers and scoreboards to generate stimulus and check results through the drivers and monitors. Typically, there will also be some global control elements for synchronizing testbench and design operation, such as clocks and resets. This presentation will outline practical steps involved in accelerating such UVM verification environments with hardware-assisted verification. In addition, this paper will discuss typical use cases of applying code and functional coverage techniques at the sub-system and system levels.
BiographyWork at NewPlus to support EVE Zebu and Coware tools for 3+ years
Work at Cadence to support Xtreme, PDIII and PXP for 4+ years
Presentation:Video Presentation
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.