Harris Zhu, Cadence

Speaker: Harris Zhu, Principal Verification Acceleration Solutions Engineer
Organisation: Cadence
Presentation Title: Guidelines to accelerate UVM-based simulations to achieve highest levels of acceleration
Abstract In a typical UVM based verification environment, a testbench contains a collection of verification components, both drivers and monitors that support interactions with various interfaces on a design. Additionally, there may be sequencers and scoreboards to generate stimulus and check results through the drivers and monitors. Typically, there will also be some global control elements for synchronizing testbench and design operation, such as clocks and resets. This presentation will outline practical steps involved in accelerating such UVM verification environments with hardware-assisted verification. In addition, this paper will discuss typical use cases of applying code and functional coverage techniques at the sub-system and system levels.
Biography Work at NewPlus to support EVE Zebu and Coware tools for 3+ years
Work at Cadence to support Xtreme, PDIII and PXP for 4+ years
Presentation: Video Presentation