Jean-Marc Forey, Synopsys 2014-07-22T10:41:07+00:00

Name:Jean-Marc Forey
Designation:Senior Staff Corporate Application Engineer
Title:C/C++ Verification Effectiveness

Abstract : C/C++ is now pervasive in design conception, either through models at different stages of the design creation or by being embedded as firmware in the design itself. A bug escaping up to production can be lead to high cost and delays in reaching the market making it mandatory to assess and improve the effectiveness of the verification of the C/C++ code.Certitude has been extended from its initial RTL focus to allow users to identify verification issues early in the design cycle.

Biography: Jean-Marc Forey has a degree from the ‘Ecole Nationale Supérieure de Physique de Strasbourg’ (1988). He has held hardware development positions in Thomson CSF, Matra Marconi Space, Philips TRT, Hewlett-Packard. He has been Senior Verification Application Engineer forSynopsys, then application engineer director in Certess. He is now back to Synopsys through the Springsoft acquisition and worked without interruption on Certitude since 2005. He is now Senior Staff Corporate Application Engineer.

DVClub Presentation                                    The recording is unavailable due to a technical problem

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.